Method and circuit for alignment of floating point...

Details Method and circuit for alignment of floating point... Method and circuit for alignment of floating point...

2005-05-17

2005-05-17

Mai, Tan V (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S209000

Reexamination Certificate

active

06895424

ABSTRACT:
The processing elements of a single instruction multiple data (SIMD) massively parallel processor (MPP) are provided with two register blocks. One register block includes logic for performing limited left shifting, while the other register block includes logic for performing limited right shifting. A method is disclosed for using the registers blocks with their associated logic to perform floating point significant alignment and normalization. The limited shifting logic occupies less die space than a full feature barrel shifter, thereby permitting a greater number of processing elements.

REFERENCES:
patent: 4807172 (1989-02-01), Nukiyama
patent: 5247471 (1993-09-01), Hilker et al.
patent: 5646875 (1997-07-01), Taborn et al.
patent: 5954790 (1999-09-01), Wong
patent: 6067556 (2000-05-01), Menezes
Research Disclosure vol. 441, article 006, Jan. 2001 (Westbourne), anon, “Unified SIMD/scalar floating point adder design”.
IBM Technical Disclosure Bulletin, No. NN8607699, Jul. 1986 (US), “Using a common barrel shifter for operand normalization, operand alignment and operand unpack and pack in floating point”, see whole document.

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