Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2005-12-13
2005-12-13
Nguyen, Linh My (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S141000
Reexamination Certificate
active
06975149
ABSTRACT:
A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.
REFERENCES:
patent: 6275079 (2001-08-01), Park
patent: 6378079 (2002-04-01), Mullarkey
patent: 6456130 (2002-09-01), Schnell
patent: 6492852 (2002-12-01), Fiscus
patent: 6539072 (2003-03-01), Donnelly et al.
patent: 6646937 (2003-11-01), Pochmuller
patent: 6670835 (2003-12-01), Yoo
patent: 2002/0017939 (2002-02-01), Okuda et al.
patent: 2002/0091958 (2002-07-01), Schoenfeld et al.
“Stub Series Terminated Logic for 2.5 V (SSTL—2) A 2.5 V Supply Voltage Based Interface Standard for Digital Integrated Circuits,” JEDEC Solid State Technology Association, Electronic Industries Alliance, JEDEC Standard No. 8-9A, pp. 1-20, Dec. 2000.
Mikhalev Vladimir
Penney Daniel B.
Schoenfeld Aaron M.
Waldrop William C.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Nguyen Linh My
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