Method and circuit for adjusting the timing of output data...

Details Method and circuit for adjusting the timing of output data... Method and circuit for adjusting the timing of output data...

2003-08-29

2004-11-16

Nguyen, Linh M. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

06819151

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to integrated circuits, and more specifically to synchronizing an external clock signal applied to an integrated circuit with internal clock signals generated in the integrated circuit in response to the external clock signal.
BACKGROUND OF THE INVENTION
In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. For example, data words are placed on a data bus of the memory device in synchronism with the external clock signal, and the memory device must latch these data words at the proper times to successfully capture each data word. To latch the applied data words, an internal clock signal is developed in response to the external clock signal, and is typically applied to storage circuits such as latches contained in the memory device to thereby clock the data words into the latches. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the data words. In the present description, “external” is used to refer to signals and operations outside of the memory device, and “internal” to refer to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different clock synchronization circuits have been considered and utilized, including delay-locked loops (DLLs), phased-locked loops (PLLs), and synchronous mirror delays (SMDs), as will be appreciated by those skilled in the art.
FIG. 1
is a functional block diagram illustrating a conventional delay-locked loop
100
including a variable delay line
102
that receives a clock buffer signal CLKBUF and generates a delayed clock signal CLKDEL in response to the clock buffer signal. The variable delay line
102
controls a variable delay VD of the CLKDEL signal relative to the CLKBUF signal in response to a delay adjustment signal DADJ. A feedback delay line
104
generates a feedback clock signal CLKFB in response to the CLKDEL signal, the feedback clock signal having a model delay D
1
+D
2
relative to the CLKDEL signal. The D
1
component of the model delay D
1
+D
2
corresponds to a delay introduced by an input buffer
106
that generates the CLKBUF signal in response to an external clock signal CLK, while the D
2
component of the model delay corresponds to a delay introduced by an output buffer
108
that generates a synchronized clock signal CLKSYNC in response to the CLKDEL signal. Although the input buffer
106
and output buffer
108
are illustrated as single components, each represents all components and the associated delays between the input and output of the delay-locked loop
100
. The input buffer
106
thus represents the delay D
1
of all components between an input that receives the CLK signal and the input to the variable delay line
102
, and the output buffer
108
represents the delay D
2
of all components between the output of the variable delay line and an output at which the CLKSYNC signal is developed.
The delay-locked loop
100
further includes a phase detector
110
that receives the CLKFB and CLKBUF signals and generates a delay control signal DCONT having a value indicating the phase difference between the CLKBUF and CLKFB signals. One implementation of a phase detector is described in U.S. Pat. No. 5,946,244 to Manning (Manning), which is assigned to the assignee of the present patent application and which is incorporated herein by reference. A delay controller
112
generates the DADJ signal in response to the DCONT signal from the phase detector
110
, and applies the DADJ signal to the variable delay line
102
to adjust the variable delay VD. The phase detector
110
and delay controller
112
operate in combination to adjust the variable delay VD of the variable delay line
102
as a function of the detected phase between the CLKBUF and CLKFB signals.
In operation, the phase detector
110
detects the phase difference between the CLKBUF and CLKFB signals, and the phase detector and delay controller
112
operate in combination to adjust the variable delay VD of the CLKDEL signal until the phase difference between the CLKBUF and CLKFB signals is approximately zero. More specifically, as the variable delay VD of the CLKDEL signal is adjusted the phase of the CLKFB signal from the feedback delay line
104
is adjusted accordingly until the CLKFB signal has approximately the same phase as the CLKBUF signal. When the delay-locked loop
100
has adjusted the variable delay VD to a value causing the phase shift between the CLKBUF and CLKFB signals to equal approximately zero, the delay-locked loop is said to be “locked.” When the delay-locked loop
100
is locked, the CLK and CLKSYNC signals are synchronized as long as the feedback delay line
104
accurately models the delays D
1
, D
2
of the input and output buffers
106
,
108
, as will be discussed in more detail below. This is true because when the phase shift between the CLKBUF and CLKFB signals is approximately zero (i.e., the delay-locked loop
100
is locked), the variable delay VD has a value of NTCK−(D
1
+D
2
) as indicated in
FIG. 1
, where N is an integer and TCK is the period of the CLK signal. When VD equals NTCK−(D
1
+D
2
), the total delay of the CLK signal through the input buffer
106
, variable delay line
102
, and output buffer
108
is D
1
+NTCK−(D
1
+D
2
)+D
2
, which equals NTCK. Thus, the CLKSYNC signal is delayed by NTCK relative to the CLK signal and the two signals are synchronized since the delay is an integer multiple of the period of the CLK signal. Referring back to the discussion of synchronous memory devices above, the CLK signal corresponds to the external clock signal and the CLKSYNC signal corresponds to the internal clock signal.
FIG. 2
is a signal timing diagram illustrating various signals generated during operation of the delay-locked loop
100
of FIG.
1
. In response to a rising-edge of the CLK signal at a time T
0
, the CLKBUF signal goes high the delay D
1
later at a time T
1
. Initially, the variable delay VD as a value VD
1
, causing the CLKDEL signal to go high at a time T
3
and the CLKSYNC signal to go high at a time T
4
. At this point, note that the positive-edge of the CLKSYNC signal at the time T
4
is not synchronized with the CLK signal, which transitions high at a time T
5
. In response to the rising-edge of the CLKDEL signal at the time T
3
, the CLKFB goes high at a time T
6
, which occurs before a positive-edge of the CLKBUF signal occurring at a time T
7
. Thus, the positive-edge of the CLKFB signal occurs at the time T
6
while the positive-edge of the CLKBUF occurs at the time T
7
, indicating there is a phase shift between the two signals. The phase detector
110
(
FIG. 1
) detects this phase difference, and generates the DCONT signal just after the time T
7
at a time T
8
which, in turn, causes the delay controller
112
(
FIG. 1
) to generate the DADJ signal to adjust the value of the variable delay VD to a new value VD
2
and thereby synchronize the CLK and CLKSYNC signals, as depicted at a time T
9
. At this point, note

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