Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular frequency control means
Reexamination Certificate
2002-08-15
2004-02-17
Callahan, Timothy P. (Department: 2816)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular frequency control means
C331S145000, C331S153000, C327S176000, C327S205000
Reexamination Certificate
active
06693495
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to current-controlled oscillators. More specifically, it relates to a CMOS-latch-based switched-current oscillator circuit.
BACKGROUND OF THE INVENTION
Current-controlled Oscillator (ICO) circuits can be used for signal generation and detection in many signal processing systems. They are often needed in Phase-Locked Loop (PLL) circuits. ICO circuits operating in a very weak current range are very useful in optical-to-electrical conversion in high-performance and low-power optical signal detection circuits, as well as in current mirrors and current-mode A/D converters.
Existing current-controlled oscillators are usually based on multi-vibrators or ring oscillators, in which multiple stages of delay elements are included. Logic gates and operational amplifiers (OpAmp) are often used as such delay elements. In ICO circuits based on logic-gate-ring, the current available to charge or discharge a capacitance of one of the gates, or, each of the gates, is adjusted in order to change the frequency of oscillation [D. Jeong et al., “Design of PLL-based clock generation circuits,” IEEE J. Solid State Circuits, Vol. SC-22, no. 2, April. 1987, pp 255-261.]. In this case, a current variation of several nano-Amperes may not be big enough to result in a significant change of the frequency.
In ICO circuits with delay elements based on OpAmps, the control current is used to adjust the circuit bias so that the gain of the OpAmps can be modified in order to adjust the frequency. In practical applications, the OpAmp-involved ICO can have drawbacks, for example, (a) the circuit structure are complex, (b) they may not function with a low supply voltage, e.g. below 1V, because the transistors, usually cascoded, need to be driven in the saturation region, and (c) they are not able to work properly when the control current is weak, e.g. in a nano-Ampere range. In most of the existing ICO, the sensitivity Kf, the ratio of frequency to current, is about several MHz per micro-Ampere or below.
Therefore, the functionality of most of the existing ICOs have a very limited sensitivity and range of the control current, as well as the supply voltages.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is provide an ICO circuit with a simpler structure than that of the state of the art.
Another object of the present invention is to provide an ICO circuit with a higher sensitivity and a better ability to operate in a nano-Ampere range or below with a very low supply voltage.
Yet another object of the present invention is to provide an ICO with very low power dissipation.
According to a first broad aspect of the present invention, there is provided an oscillator circuit comprising: a latch comprising two logic inverters to maintain a switch state for a determined duration, the latch having two complementary output voltages; a differential switch pair comprising a first and a second switch controlled by the two complementary output voltages respectively to steer a control current to a first and a second node alternatively; a third and fourth switch driven on by a high level voltage at one of the first and second node to set and reset the latch; and a fifth and sixth switch controlled by the two complementary output voltages respectively to pull down voltages at the first and second node alternatively, wherein the first and fifth switch are controlled by a same control signal and the second and sixth switch are controlled by a same control signal; whereby the frequency of switching is a function of the capacitance of the first and second node and the control current.
Preferably, the first and second switches are PMOS transistors, the third, fourth, fifth, and sixth switches are NMOS transistors, and the logic inverters employed in the latch are complementary CMOS inverters.
According to a second broad aspect of the present invention, there is provided a method for current-controlled oscillation comprising: providing a latch to maintain a state for a determined duration and having two complementary output voltages; switching alternatively a control current from a first node to a second node representing a set and reset of said latch; and controlling said switching using said two complementary output voltages.
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IEEE 1987, Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987 Design of PLL-Based Clock Generation Circuits, Deog-Kyoon Jeong et al. pp. 255-261.
IEEE, 1999, Differential 0.35 &mgr;m CMOS Circuits for 622MHz/933 MHz Monolithic Clock and Data Recovery Applications, H. Djahanshahi et al. Dept. of Electrical and Computer Engineering, University of Toronto, pp. II-93-II-96.
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(Ogilvy Renault)
Anglehart James
Callahan Timothy P.
Luu An T.
Valorbec, Limited Partnership
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