Method and circuit device to control a memory

Details Method and circuit device to control a memory Method and circuit device to control a memory

1995-04-14

1996-11-19

Beausoliel, Jr., Robert W.

Excavating

371 491, G06F 1110, H03H 1300

Patent

active

055770550

ABSTRACT:
A method and a circuit device control insertion and storage of digital information in a memory and retrieval of the information from the memory. The method and circuit device ensure the digital information is correctly read out of the memory in the form of a number of coordinated bit positions, and the digital information is used to control one or several functions. The information intended to be inserted into the memory is given an address belonging to the memory. First control-sum-carrying bit positions are calculated from the bit positions of the digital information and their values coming into the memory according to a selected evaluation function. The bit positions of the digital information are stored in an address within the memory, and the first control-sum-carrying bit positions are stored in an address within a control memory. Second control-sum-carrying bit positions are calculated when the bit positions of the digital information stored in the address in the memory are read out according to the selected evaluation function. The bit positions of the read information, and their values, are accepted as correct, and a circuit is activated through a signal on a conductor, if a following comparison between the first and second control-sum-carrying bit positions shows that they are identical.

REFERENCES:
patent: 4019033 (1977-04-01), Parmet
patent: 4271521 (1981-06-01), Mahmood
patent: 4692893 (1987-09-01), Casper
patent: 4809278 (1989-02-01), Kim et al.
patent: 5477553 (1995-12-01), Kong
J. D. Dixon et al., "Parity Mechanism for Detecting Both Address and Data Errors," IBM Technical Bulletin, vol. 24, No. 1B, p. 794 (Jun. 1981).

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