Method and circuit configuration of the parallel input of data i

Details Method and circuit configuration of the parallel input of data i Method and circuit configuration of the parallel input of data i

1988-03-16

1989-12-05

Smith, Jerry

Excavating

371 27, 365201, G11C 2900

Patent

active

048857483

ABSTRACT:
A method and circuit configuration for the parallel input of data items in the form of a test pattern into a block of a semiconductor memory having a plurality of storage cells. For test purposes, data items are simultaneously input in parallel into the storage cells.

REFERENCES:
patent: 4044340 (1977-08-01), Itoh
patent: 4055754 (1977-10-01), Chesley
Integration To VLSI Journal, vol. 2, No. 4, Dec. 1984, pp. 309-330, Elsevier Science Publishers B.V.
Amsterdam, NL; K. K. Saluja et al: "Testable Design of Large Random Access Memories", p. 321, lines 7-20, p. 324, lines 17-28, Figures 8, 9, and 11.
IEEE Transactions On Electron Devices, vol. Ed-32, No. 2, Feb. 1985, pp. 508-515, IEEE, New York, U.S.; Y. You et al.: "A Self-Testing Dynamic RAM Chip"; p. 511. Left col., line 26-Right col., line 14, p. 514, left col., lines 22-26.
IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 635-642, IEEE, New York, U.S.; H. Mc Adams et al.: "A 1-Mbit CMOS dynamic RAM with design -for test functions", p. 638, Right col., lines 35-55; and FIG. 7.

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