Method and circuit arrangement for the compensation of echo sign

Details Method and circuit arrangement for the compensation of echo sign Method and circuit arrangement for the compensation of echo sign

1984-07-26

1987-09-22

Rubinson, Gene Z.

Multiplex communications

Wide area network

Packet switching

379411, H04B 320

Patent

active

046959980

ABSTRACT:
For the compensation of echo signals occuring in the course of the duplex transmission of digital signals by the dual channel system in signal transmission equipment provided with an echo compensator, the equipment is designed so that the clock pulses emitted by a timing generator for the transmission of the digital signals can be shifted in phase by predetermined phase grid steps. When a change in the phase position of the clock pulses takes place within one phase grid step, correction signals are generated, with the phase position that has been accurately set in each case being maintained. These correction signals are subtracted, together with the compensation signals emitted by the echo compensator for the compensation of the echo signals, from the digital signals received together with the echo signals.

REFERENCES:
patent: 4072830 (1978-02-01), Gitlin et al.
patent: 4074086 (1978-02-01), Falconer et al.
patent: 4539674 (1985-09-01), Carlqvist et al.
IBM Technical Disclosure Bulletin, vol. 12, No. 7, Dec. 1969, p. 980, "Binary Synchronous Communication Internal Clock.
IEEE, vol. Com-30, No. 9, Sep. 1982, pp. 2074-2082, T. Suzuki et al., "Line Equalizer for a Digital Subscriber Loop Employing Switched Capacitor Technology".
IEEE, vol. Com-30, No. 9, Sep. 1982, pp. 2095-2108, O. Agazzi et al., "Large-Scale Integration of Hybrid Method Digital Subscriber Loops".

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