Electricity: motive power systems – Limitation of motor load – current – torque or force
Reexamination Certificate
2000-12-01
2003-07-01
Nappi, Robert E. (Department: 2837)
Electricity: motive power systems
Limitation of motor load, current, torque or force
C318S254100, C318S432000, C318S434000, C318S599000, C361S087000, C361S093100
Reexamination Certificate
active
06586899
ABSTRACT:
FIELD AND BACKGROUND OF THE INVENTION
The invention relates to a method for switching on a power output stage, in particular for electric motors having a high current draw, and to a circuit arrangement for carrying out the method.
Motor vehicles increasingly use electric motors which draw a very high current on starting, braking or when changing direction. Such electric motors are used, for example, for window winders or to provide valve travel in the internal combustion engine. In order to ensure a constant supply voltage for the output stage when such high current peaks occur, which may be, for example, approximately 100 A, the output stage can be buffered, generally by a number of electrolytic capacitors, which have a high capacitance of, for example, 3000 &mgr;F and a very low internal resistance of a few milliohms. A relay which is used to switch the output stage on and off is loaded with a very high current pulse, for example 200 A, on switching on owing to the extremely low internal resistance of the capacitors. This severe load on the relay necessitates an appropriate design, even though it can be designed for lower currents for actual operation.
SUMMARY OF THE INVENTION
The object of the present invention is to specify a method and a circuit arrangement by means of which such high current pulses on switching on can be avoided, so that it is possible to use a relay designed for lower currents.
According to the invention, the object is achieved in that at least one capacitor, which is provided for buffering the power output stage, is first of all initially charged with a limited current, and is then charged to approximately the operating voltage of the power output stage.
The invention has the advantage that the initial charging of the capacitor prevents damaging inrush currents from flowing. The operating voltage is not applied until the voltage across the capacitor reaches a level at which damaging inrush currents no longer flow.
The change from the initial charging phase to the operating voltage can in this case be carried out in various ways.
In one refinement, the at least one capacitor is charged with the limited current in a predetermined time.
As an alternative to this, the at least one capacitor is initially charged with the limited current until the voltage across the capacitor reaches a predetermined value.
In another development of the invention, the at least one capacitor is charged until the difference between the operating voltage and the voltage across the at least one capacitor falls below a predetermined value.
Advantageously, once the limited current has been switched off, a change is made to the full operating voltage of the power output stage.
In the circuit arrangement according to the invention, the object is achieved in that the output stage and at least one buffer capacitor connected in parallel with it are connected via a relay to an operating voltage source, in that a current source which supplies a limited current is connected to the at least one capacitor, bypassing the relay, and in that a delay device is provided which does not switch the relay on until the at least one capacitor has been charged approximately to the operating voltage by means of the current source.
The circuit arrangement according to the invention avoids the need to use an expensive high-load relay and in the process reduces the formation of sparks on switching on, reduces the load on the relay contacts, and thus lengthens the life of the relay. A further advantage of the circuit arrangement according to the invention is that it avoids the electromagnetic interference associated with high current pulses.
The electronic complexity to reduce the circuit arrangement according to the invention is extremely low, particularly if the current source and the relay can be controlled by a controller. A controller which is required in any case to control the output stage can frequently be used for this purpose. However, this does not preclude the delay device being produced using conventional circuit technology. The circuit arrangement according to the invention, which is generally installed in the same housing as the output stage and the capacitors, requires no additional complexity whatsoever, such as wiring or plug connectors.
In one advantageous refinement of the invention, the relay is switched on at a predetermined time after the current source has been switched on. This can be achieved particularly easily and leads to a considerable reduction in the inrush current pulse.
In detail, and depending on the Circumstances, it may also be possible to use another advantageous refinement in which the relay is not switched on until the voltage across the at least one capacitor reaches a predetermined value.
An even greater reduction in the inrush current pulse can be achieved with a further refinement, in which the relay is not switched on until the difference between the operating voltage and the voltage across the at least one capacitor falls below a predetermined value.
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patent: 4456865 (1984-06-01), Robertson, Jr. et al.
patent: 5923135 (1999-07-01), Takeda
patent: 5962996 (1999-10-01), Goto et al.
patent: 6194865 (2001-02-01), Mitsui et al.
patent: 6330140 (2001-12-01), Wilson-Jones et al.
patent: 2435504 (1976-02-01), None
Farber Martin A.
Mannesmann VDO AG
Nappi Robert E.
Smith Tyrone
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