Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2006-09-19
2006-09-19
Rodriguez, Paul L. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S018000, C324S076820, C324S076540
Reexamination Certificate
active
07110932
ABSTRACT:
A method and circuit arrangement for determining performance of a digital circuit to a critical degree by the transit time of signals of the longest signal path, also called the critical path. Since the signal transit time is influenced by the operating voltage, by regulating the operating voltage, to compensate for the effects caused by temperature and process fluctuations on the signal transit time in the digital circuit. In particular, the operating voltage can be regulated as a function of the signal transit time in such a way that a required minimum operating frequency can always be achieved. To determine signal transit time, the digital circuit has associated with it a number of replicas of the critical path in the digital circuit upon which the signal transit time is determined. In order to determine the transit time, the signal path replicas are exposed to the same operating conditions as the digital circuit. Also, to allow a safety margin to be obtained, the signal path replicas have additional circuit elements that further slow down the signal transit times on the signal path replicas. Further, the mean of the transit times on the signal path replicas is determined.
REFERENCES:
patent: 4980586 (1990-12-01), Sullivan et al.
patent: 5365463 (1994-11-01), Donath et al.
patent: 5386150 (1995-01-01), Yonemoto
patent: 5438259 (1995-08-01), Orihashi et al.
patent: 5451861 (1995-09-01), Giebel
patent: 5457719 (1995-10-01), Guo et al.
patent: 5845109 (1998-12-01), Suzuki et al.
patent: 5870404 (1999-02-01), Ferraiolo et al.
patent: 6313622 (2001-11-01), Seki et al.
patent: 6477659 (2002-11-01), Ho
patent: 6535735 (2003-03-01), Underbrink et al.
patent: 2004/0019450 (2004-01-01), Berthold et al.
patent: 39 38 459 (1989-11-01), None
patent: 42 33 850 (1992-10-01), None
patent: 692 24 270 (1992-11-01), None
patent: 60041892 (1985-03-01), None
Bowman, K.A. et al. “Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution.” IEEE Int'l Solid-State Circuits Conf., 2001, Feb. 7, 2001. pp. 278-279.
Bowman, K.A. et al. “Impact of Extrinsic and Intrinsic Parameter Fluctuations on CMOS-circuit Performance.” IEEE Journal of Solid State Circuits. vol. 35, Issue 8, pp. 1186-1193.
Carley, L.R. and A. Agrawal. “A Completely On-Chip Voltage Regulation Technique for Low Power Digital Circuits.” Proc. 1999 Int'l Symposium on Low Power Electronics and Design (ISLPED '99). 1999. pp. 109-111.
Dragone, N. et al. “An Adaptive On-Chip Voltage Regulation Technique for Low-Power Applications.” Proc. of the 2000 Int'l Symposium on Low Power Electronics and Design (ISLPED '00). 2000. pp. 20-24.
Berthold Joerg
Lorch Henning
Infineon Technologies AG.
Marshall & Gerstein & Borun LLP
Rodriguez Paul L.
Sharon Ayal
LandOfFree
Method and circuit arrangement for regulating the operating... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and circuit arrangement for regulating the operating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and circuit arrangement for regulating the operating... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3566078