Method and circuit arrangement for picture-in-picture fade-in

Details Method and circuit arrangement for picture-in-picture fade-in Method and circuit arrangement for picture-in-picture fade-in

2005-03-29

2005-03-29

Kostak, Victor R. (Department: 2614)

Television

Basic receiver with additional function

For display of additional information

C348S511000, C348S718000

Reexamination Certificate

active

06873370

ABSTRACT:
A method and a circuit arrangement for picture-in-picture insertion are described, in which, in order to prevent a write operation from being overtaken by a read operation and also to avoid the associated picture disturbances, a field is stored under an address which precedes a previous field by a number of N lines. A read address is then shifted to the same line of the older field in the event of a minimum distance to a write address being undershot.

REFERENCES:
patent: 4249213 (1981-02-01), Imaide et al.
patent: 4821086 (1989-04-01), McNeely et al.
patent: 5369442 (1994-11-01), Braun
patent: 5434625 (1995-07-01), Willis
patent: 6160590 (2000-12-01), Shimizu et al.
patent: 29 27 133 (1980-04-01), None
patent: 195 34 781 (1995-09-01), None
patent: 0 304 236 (1989-02-01), None
patent: 0 411 548 (1991-02-01), None
patent: 0 471 878 (1992-02-01), None
patent: 2 215 954 (1989-09-01), None

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