Method and cascading differential signal circuit for...

Details Method and cascading differential signal circuit for... Method and cascading differential signal circuit for...

2006-10-31

2006-10-31

Shalwala, Bipin (Department: 2629)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

Reexamination Certificate

active

07129924

ABSTRACT:
A cascading differential signal circuit. The processor outputs a differential signal. The data-bus transmits the differential signal. Each driving IC comprises a data receiving circuit, a terminal resistor, an output terminal and an analog-digital converter. The data receiving circuit is coupled to the data-bus for receiving the differential signals and encoding a digital signal. The terminal resistor is coupled to the data receiving circuit for acquiring an impedance match with the data-bus to transmit the differential signals. The output terminal is coupled to the terminal resistor for outputting the differential signals. The analog-digital converter is coupled to the data receiving circuit for converting the digital signal to an analog signal.

REFERENCES:
patent: 2001/0013850 (2001-08-01), Sakaguchi et al.
patent: 2003/0038771 (2003-02-01), Sunohara
patent: 2003/0193350 (2003-10-01), Chow

Affiliated with

Also associated with

Rating

Method and cascading differential signal circuit for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and cascading differential signal circuit for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and cascading differential signal circuit for... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3676421