Method and CAD system for calculating semiconductor circuit resi

Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing

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700121, 39550002, G06F 1900

Patent

active

060320826

ABSTRACT:
A CAD system is used to design a semiconductor circuit having wiring layers and contact holes that connect wires formed on the wiring layers to each other. The CAD system has an individual resistance calculation block for calculating and storing the resistances of the contact hole and the wires which are connected to the contact hole to form a wiring path. A summation block sums up the calculated resistances, to provide the resistance of the wiring path. An individual resistance calculation block calculates and stores, as the resistance of the contact hole, a first resistance in contact with a first wiring layer, a second resistance in contact with a second wiring layer, an interlayer resistance, and a combination of them. The summation block calculates the resistance of the wiring path using, as the resistance of the contact hole, the first resistance when the wires of the wiring path are on the first wiring layer, the second resistance when the wires of the wiring path are on the second wiring layer, and the sum of half of the first resistance, half of the second resistance, and the interlayer resistance when the wires of the wiring path are on the first and second wiring layers.

REFERENCES:
patent: 5404309 (1995-04-01), Yamamoto et al.
patent: 5551014 (1996-08-01), Yoshida et al.
patent: 5598348 (1997-01-01), Rusu et al.
patent: 5872952 (1999-02-01), Tuan et al.

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