Excavating
Patent
1997-03-24
1999-06-15
Nguyen, Hoa I.
Excavating
371 226, 371 27, G01R 3128
Patent
active
059129018
ABSTRACT:
A built-in self-test (BIST) apparatus and method for testing an integrated circuit are disclosed which enable capture of failure data for a selected failure. The BIST apparatus comprises a clock generator, which generates at least a first clock signal, and a built-in self-tester, which applies predetermined input data patterns to the integrated circuit in response to the first clock signal. In addition, the BIST apparatus includes a data comparator for comparing output data received from the integrated circuit with expected output data. The data comparator detects a failure within the integrated circuit when the output data received from the integrated circuit differs from the expected output data. The BIST apparatus further includes a clock controller that disables the first clock signal in response to the detection of a selected occurrence of a failure. By enabling testing of the integrated circuit to be halted upon the occurrence of a selected failure, failure analysis of the integrated circuit is enhanced.
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Adams R. Dean
Ouellette Michael R.
Prilik Ronald J.
Dillon Andrew J.
International Business Machines - Corporation
Nguyen Hoa I.
Russell Brian F.
Skladony William P.
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