Method and built-in self-test apparatus for testing an integrate

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371 226, 371 27, G01R 3128

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active

059129018

ABSTRACT:
A built-in self-test (BIST) apparatus and method for testing an integrated circuit are disclosed which enable capture of failure data for a selected failure. The BIST apparatus comprises a clock generator, which generates at least a first clock signal, and a built-in self-tester, which applies predetermined input data patterns to the integrated circuit in response to the first clock signal. In addition, the BIST apparatus includes a data comparator for comparing output data received from the integrated circuit with expected output data. The data comparator detects a failure within the integrated circuit when the output data received from the integrated circuit differs from the expected output data. The BIST apparatus further includes a clock controller that disables the first clock signal in response to the detection of a selected occurrence of a failure. By enabling testing of the integrated circuit to be halted upon the occurrence of a selected failure, failure analysis of the integrated circuit is enhanced.

REFERENCES:
patent: 4404519 (1983-09-01), Westcott
patent: 4414665 (1983-11-01), Kimura et al.
patent: 4549295 (1985-10-01), Purvis
patent: 4769761 (1988-09-01), Downes et al.
patent: 4841485 (1989-06-01), Prilik et al.
patent: 4872168 (1989-10-01), Aadsen et al.
patent: 4962500 (1990-10-01), Sakagawa
patent: 4972144 (1990-11-01), Lyon et al.
patent: 5051996 (1991-09-01), Bergeson et al.
patent: 5132635 (1992-07-01), Kennedy
patent: 5132973 (1992-07-01), Obermeyer
patent: 5138619 (1992-08-01), Fasang et al.
patent: 5173906 (1992-12-01), Dreibelbis et al.
patent: 5301156 (1994-04-01), Talley
patent: 5301197 (1994-04-01), Yamede et al.
patent: 5351232 (1994-09-01), Yamashita
patent: 5381087 (1995-01-01), Hirano
patent: 5383195 (1995-01-01), Spence et al.
Jaber, T., "AC Array . . . ," IBM Tech. Disclosure Bulletin, vol. 35, No. 1B, Jun. 1992.
Jabor, T.K., "Array Built-In . . . ," IBM Tech. Disclosure Bulletin, vol. 34, No. 1, Jun. 1991.
AK Williams, T.W., "High-Speed, Low . . . " IBM Tech. Disclosure Bulletin, vol. 23, No. 8, Jan. 1981.

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