Method and arrangement for testing mega-bit memory modules with

Details Method and arrangement for testing mega-bit memory modules with Method and arrangement for testing mega-bit memory modules with

1987-10-05

1989-06-20

Atkinson, Charles E.

Excavating

371 24, G01R 3128

Patent

active

048415251

ABSTRACT:
For testing memory modules of the mega-bit generation in the multi-bit test mode with arbitrary test patterns, whereby m cells of the cell field are simultaneously tested, at least one m-dimensional test word is generated in test word registers additionally integrated in the memory module MBS, with at least one test word being subsequently mapped onto the cells of an m-dimensional cell group or of a plurality of cell groups. Simultaneously, the test word or words are supplied to a comparison logic for comparing these to the test words upon readout of the test contents of a cell group and generating a good or bad signal for indicating the result of this inverse mapping, dependent on the comparison.

REFERENCES:
patent: 4195770 (1980-04-01), Benton et al.
patent: 4319355 (1982-03-01), Mollier
patent: 4414665 (1983-11-01), Kimura et al.
patent: 4541090 (1985-09-01), Shiragasawa
patent: 4667330 (1987-05-01), Kumagai
patent: 4752929 (1988-06-01), Kantz

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