Method and arrangement for testing a power output stage

Details Method and arrangement for testing a power output stage Method and arrangement for testing a power output stage

2007-07-10

2007-07-10

Nguyen, Khanh Van (Department: 2817)

Amplifiers

With amplifier condition indicating or testing means

C330S146000, C330S251000

Reexamination Certificate

active

10842119

ABSTRACT:
An arrangement for testing a power output stage, with the power output stage includes at least one half bridge with an upper semiconductor switch and a lower semiconductor switch connected in series and to which an operating voltage is applied. A junction point between the semiconductor switches of the at least one half bridge forms an output. A control device performs a test to determine whether the voltage at the output is within a predetermined central tolerance band when the semiconductor switches are not switched on, a test to determine whether the voltage at the output is within a predetermined upper tolerance band when the upper semiconductor switch is switched on, and a test to determine whether the voltage at the output is within a predetermined lower tolerance band when the lower semiconductor switch is switched on. The power output stage is identified as being sound when all of the output voltages are within the respective tolerance bands.

REFERENCES:
patent: 6586899 (2003-07-01), Joch
patent: 6661285 (2003-12-01), Pompei et al.
patent: 7132884 (2006-11-01), Ohkuri et al.

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