Method and arrangement for setting a frequency

Details Method and arrangement for setting a frequency Method and arrangement for setting a frequency

2001-06-28

2003-12-09

Lam, Tuan T. (Department: 2816)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S002000, C327S147000, C327S148000, C327S156000

Reexamination Certificate

active

06661293

ABSTRACT:

The invention relates to a method for bringing a phase-locked loop into lock when the frequency setting of the loop changes. The invention further relates to an arrangement for bringing a phase-locked loop into lock.
The phase-locked loop or PLL is a circuit in which feedback is used to, first, force the frequency of the oscillator in the circuit to follow the frequency of the input signal and, second, make the phase difference between the two waveforms in question constant. If the input signal is continuously varying, the PLL can be arranged to “seize” a certain frequency component. In telecommunications technology, the PLL is widely used for various synchronization purposes and frequency synthesis, for example. The latter is used in multichannel radio devices, such as mobile stations, to set the carrier frequency when selecting a channel.
There are very many known circuit implementations of the PLL.
FIG. 1
shows an example of known circuit used for frequency synthesis. It includes the basic parts of the PLL, namely a phase difference detector
110
, filter
120
and a voltage-controlled oscillator (VCO)
130
. Connected to the first input R of the phase difference detector is a reference divider
141
to which a reference clock CK
ref
is brought from an external oscillator, the frequency f
ref
of the reference clock keeping constant with great accuracy. Hereinafter the reference divider will be called the r-divider for short. The division factor of the r-divider is m, which corresponds to an output frequency of f
r
. The loop is produced by the phase difference detector controlling the charge pump
150
, the charge pump controlling the filter
120
and the filter controlling the VCO. Further, the output signal of the VCO is taken to a prescaler
142
, the output signal of the prescaler is taken to a second divider
144
, and the output signal of the latter is taken to the second input V of the phase difference detector. Hereinafter the said second divider will be called the v-divider for short. The frequency of the VCO is f
VCO
, the output frequency of the prescaler is f′ and the output frequency of the v-divider is f
v
. In connection with the prescaler
142
and v-divider
144
there is an auxiliary divider
143
the clock input of which is connected to the prescaler output. The division ratio of the v-divider is n, and the division ratio of the auxiliary divider is a. These three counters are interconnected in a known manner such that during the v-divider cycle the prescaler divides its input frequency by a number p for a clock cycle amount n−a of the auxiliary divider. During the rest of the v-divider cycle, i.e. for the duration of a clock cycle amount a of the auxiliary divider, the prescaler divides the frequency by a number p+1. Thus the number of VCO cycles during the v-divider cycle is
p(n−a)+(p+1)a.
Considering that the input frequencies f
r
and f
v
of the phase difference detector are forced equal, we get
f
VCO
=(
pn+a
)
f
r
=f
0
+af
r
.
In the latter expression, f
0
=pnf
r
. By selecting suitable parameter values m, n, p and a, we get a desired lower limit f
0
and a minimum frequency step f
r
of a desired magnitude for the VCO frequency. Numbers a and n can be loaded by the software in the counters in question and can be used to change the frequency when necessary.
The phase difference detector
110
has got two outputs U and D. When the phase of the first input R leads the second input V, there appear “0” pulses at the frequency of f
r
at the output U, the length of the said pulses being proportional to the phase difference between the input signals. Output D remains in state “0”. When the phase of the first input R lags behind the second input V, there appear “1” pulses at the frequency of f
r
at the output D, the length of the said pulses being proportional to the phase difference between the input signals. Output U remains in state “1”. Output U controls the upper switch component Q
1
in the charge pump
150
in such a manner that the Q
1
passes during a U pulse the current of the current source J
1
, connected in series with the switch Q
1
, from the positive terminal of the operating voltage supply to the filter
120
. Output D controls the lower switch component Q
2
in the charge pump
150
in such a manner that the Q
2
passes during a D pulse the current of the current source J
2
, connected in series with the switch Q
2
, from the filter
120
to ground. In the example of
FIG. 1
the filter
120
includes a series connection of a capacitor C
1
and resistor R
1
as well as a capacitor C
2
in parallel with the said series connection. Filter component values are chosen such that the filter impedance at frequency f
r
is determined only by resistance R
1
. At lower frequencies, capacitance C
1
raises the magnitude of the filter impedance, and at higher frequencies, capacitance C
2
lowers the magnitude of the filter impedance. The effect of the capacitances may also be expressed by saying that they smooth out the shape of the voltage coming from the charge pump. When the PLL is in operation, the filter voltage v
c
has a certain positive level. The said U pulses raise this voltage level and the said D pulses lower it. The oscillator
130
is controlled by the voltage v
c
. The increase in the control voltage results in an increase in the frequency f
VCO
and vice versa.
A disadvantage of circuits like those described above is that the locking of the loop may take too long a time when the frequency is changed. A high locking speed is required e.g. when transmitting data in several time slots belonging to different frequency division channels, whereby changes between channels are sometimes relatively rapid. An insufficient speed in the loop may be caused by the slowness of the filter in the circuit. However, making the filter faster would degrade the noise characteristics of the loop. On the other hand, the insufficient speed of the loop may be caused by too low input frequency in the phase difference detector. As known, frequency correction advances in steps: Each individual subcorrection is based on a comparison carried out during one cycle of the input frequency f
r
.
The settling speed of the VCO frequency can in a known manner be increased using a so-called fractional-N structure. In such a structure the output frequency of the VCO can be changed in steps that are only a certain fraction of the reference input frequency of the phase difference detector. The reference input frequency may then be greater compared to a corresponding structure according to
FIG. 1
, which means a higher settling speed. A disadvantage of the fractional-N circuit is its complicity, resulting in a relatively large size and high manufacturing cost.
In the article “Fast Settling PLL Frequency Synthesizer Utilizing the Frequency Detector Method Speedup Circuit”, published in the IEEE Transactions on Consumer Electronics, Vol. 43 No 3 August 1997, there is presented a circuit for increasing the settling speed of the loop.
FIG. 2
shows the block diagram of the structure. It is based on a structure like the one shown in
FIG. 1
, comprising an r-divider
241
, phase difference detector
210
, charge pump
250
, low-pass filter
220
, voltage-controlled oscillator
230
and a divider unit
240
. The latter corresponds to the dividers
142
,
143
and
144
in FIG.
1
. To speed up the settling of the frequency the circuit further includes a block called ‘frequency detector method speedup circuit’, FDMSC for short, and a switch SWI for the low-pass filter. The input signals of the FDMSC are the same output signals R and V of the r-divider and divider unit
240
that are also taken to the phase difference detector, and the output signals U and D of the phase difference detector. The output signals of the FDMSC are the control signals U′ and D′ of the charge pump
250
, the reset signal of the r-divider and divider unit
240
, and the control signal for the switch SWI. When the loop is in

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