Method and arrangement for reducing interference

Details Method and arrangement for reducing interference Method and arrangement for reducing interference

2001-08-28

2003-05-20

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

C341S101000, C341S144000, C341S155000

Reexamination Certificate

active

06567020

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a method for reducing interference created in an output signal in connection with signal conversion.
BACKGROUND OF THE INVENTION
It is more likely for data transmission to cause various forms of interference when a higher transmission rate is used. Fast bus structures in particular cause interference, as high clock frequencies are used in signal transmission. The use of a serial bus in particular creates noise and interference to the apparatuses close to the bus, when the data rate of the signals to be-transmitted on the bus increases too much.
BRIEF DESCRIPTION OF THE INVENTION
It is an object of the invention to provide a method and an arrangement so as to solve the above problems. This is achieved with the method of the type set forth in the preamble, characterized in that in order to carry out the method two sets of process steps can be employed, whereof at least one is performed in this method, the first set of process steps comprises the step of generating a digital modulated input signal in serial mode which is converted into parallel mode, and simultaneously several digital signals are transferred using a clock signal for conversion into analogue output signals, the frequency of the clock signal being lower than the frequency of the clock signal used in serial-mode signal transmission, the second set of process steps comprises the step of receiving analogue input signal, which is converted into several parallel digital output signals which are simultaneously transferred using a clock signal for conversion into serial mode signals, the frequency of the clock signal being lower than the frequency of the clock signal used in serial-mode signal transmission.
The invention also relates to an arrangement for reducing interference in an output signal in connection with signal conversion.
The arrangement of the invention is characterized in that the arrangement may employ two structural sets, whereof the arrangement comprises at least one, the first structural set comprises a modulator arranged to modulate the signal, and a DA converter arranged to convert the serial-mode input signal arriving from the modulator into an analogue output signal, and a serial/parallel converter arranged to convert the modulated signal into parallel mode, and a divider for generating a clock signal, the frequency of the clock signal generated by the divider being lower than the frequency of the clock signal used in serial-mode input signal transmission, and the divider is arranged to simultaneously clock several signals to the DA converter, and the second structural set comprises an AD converter arranged to convert an analogue input signal into several parallel digital output signals, and a parallel/serial converter arranged to receive several simultaneously arriving digital signals for conversion into serial mode signals using a clock signal, the frequency of which being lower than the frequency of the clock signal used in serial-mode signal transmission.
The preferred embodiments of the invention are disclosed in the dependent claims.
The invention is based on the idea to convert a signal into parallel mode, and thereafter to perform the required conversion for the signal, whereby a lower clock frequency can be used in signal transmission.
Several advantages can be achieved with the method and arrangement of the invention. A serial-mode signal is converted into parallel mode before carrying out a DA conversion, whereby the clock frequency of the clock signal used in analogue signal transmission can be reduced. Another advantage is that several signals can be simultaneously transmitted to a DA converter using a clock signal, the frequency thereof being lower than the frequency of the clock signal used in serial-mode signal transmission, in which case interference possibly created to the converted analogue signal can be reduced.
The arrangement of the invention is easy to implement, for example using discrete components. The analogue signals are transferred to a bus, which may also reduce the interference caused by the signals to be transmitted. A clock signal, having a frequency that is lower than the frequency of the clock signal used in serial-mode signal transmission, is used for transferring each signal on the bus.


REFERENCES:
patent: 4670792 (1987-06-01), Dureigne et al.
patent: 4908838 (1990-03-01), Mizoguchi
patent: 4983965 (1991-01-01), Doi et al.
patent: 5050474 (1991-09-01), Ogawa et al.
patent: 5136587 (1992-08-01), Obana et al.
patent: 5333136 (1994-07-01), Ahn
patent: 5541665 (1996-07-01), Urata et al.
patent: 6031473 (2000-02-01), Kubinec
patent: 6160859 (2000-12-01), Martin et al.
patent: 6172632 (2001-01-01), Carter, IV
patent: 6202108 (2001-03-01), Autechaud et al.
patent: 0092083 (1983-10-01), None
patent: WO 00/70768 (2000-11-01), None
Patent Abstracts of Japan Publication No. JP 06085762.
Patent Abstracts of Japan Publication No. JP 07123368.
Patent Abstracts of Japan Publication No. JP 07212229.

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