Method and arrangement for generating an output clock signal...

Details Method and arrangement for generating an output clock signal... Method and arrangement for generating an output clock signal...

2005-08-01

2008-09-02

Pascal, Robert J. (Department: 2817)

Oscillators

Combined with particular output coupling network

C327S153000, C327S161000, C375S326000

Reexamination Certificate

active

07420430

ABSTRACT:
Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals.A method and an arrangement are provided for generating an output clock signal (o), in which a plurality of input clock signals (s, c) that have a predetermined phase relationship to one another, are weighted with respective weighting factors (A,1-A), and in which the weighted input clock signals (s′, c′) are added in order to generate a summated clock signal (i). The summated clock signal (i) is integrated in an integrator (8) and optionally amplified in order to generate the output clock signal (o). An output clock signal (o) with an adjustable phase relation can be generated with such a method and such an arrangement, in which the requirements placed on the input clock signals are less stringent.

REFERENCES:
patent: 6417712 (2002-07-01), Beards et al.
patent: 6539072 (2003-03-01), Donnelly et al.
patent: 6831497 (2004-12-01), Koh et al.
patent: 6995593 (2006-02-01), Cucchi et al.
patent: 6995617 (2006-02-01), Citta et al.
patent: 7057450 (2006-06-01), Koike
patent: 2003/0002607 (2003-01-01), Mooney et al.
patent: 0 909 035 (1999-04-01), None
patent: 1 351 429 (2003-10-01), None

Affiliated with

Also associated with

Rating

Method and arrangement for generating an output clock signal... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and arrangement for generating an output clock signal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and arrangement for generating an output clock signal... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3968042