Method and arrangement for generating an output clock signal...

Details Method and arrangement for generating an output clock signal... Method and arrangement for generating an output clock signal...

2008-09-02

2008-09-02

Pascal, Robert J. (Department: 2817)

Oscillators

Combined with particular output coupling network

C327S153000, C327S161000, C375S326000

Reexamination Certificate

active

11194494

ABSTRACT:
Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals.A method and an arrangement are provided for generating an output clock signal (o), in which a plurality of input clock signals (s, c) that have a predetermined phase relationship to one another, are weighted with respective weighting factors (A,1-A), and in which the weighted input clock signals (s′, c′) are added in order to generate a summated clock signal (i). The summated clock signal (i) is integrated in an integrator (8) and optionally amplified in order to generate the output clock signal (o). An output clock signal (o) with an adjustable phase relation can be generated with such a method and such an arrangement, in which the requirements placed on the input clock signals are less stringent.

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patent: 1 351 429 (2003-10-01), None

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