Method and arrangement for generating a correction signal for a

Details Method and arrangement for generating a correction signal for a Method and arrangement for generating a correction signal for a

1988-10-31

1990-11-20

Olms, Douglas W.

Pulse or digital communications

Spread spectrum

Direct sequence

375119, H04L 702

Patent

active

049724436

ABSTRACT:
A method and arrangement for generating a correction signal for a digital clock recovery circuit. This method cost effectively provides phase sensors that can be realized in integrated technology. In a sample-and-hold circuit, an auxiliary data clock (DHT1) that is valid as a recovered clock of a digital signal (DS1) and whose clock frequency is somewhat higher or lower than the bit rate of this digital signal (DS1) is sampled by the latter. Then a trailing edge of a pulse of this auxiliary data clock (DHT1) is identified by a status change. The sample-and-hold circuit then outputs a correction request signal (K1) that releases a correction signal (K) in a following circuit, this correction signal (K) being synchronous with the auxiliary data clock (DHT1). This method is utilized in digital clock recovery equipment.

REFERENCES:
patent: 4348762 (1982-09-01), Shiun et al.
patent: 4584695 (1986-04-01), Wong et al.
patent: 4715050 (1987-12-01), Tanaka et al.
patent: 4780889 (1988-10-01), Ley et al.
patent: 4841548 (1989-06-01), Volejnik

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