Method and architecture for reducing flickers using one FIFO vid

Details Method and architecture for reducing flickers using one FIFO vid Method and architecture for reducing flickers using one FIFO vid

1998-04-28

1999-08-10

Faile, Andrew I.

Television

Format conversion

Progressive to interlace

348447, 348607, 348910, H04N 701, H04N 521

Patent

active

059366753

ABSTRACT:
A system for reducing flickers in converting non-interlaced video signals to interlaced video signals is disclosed. The non-interlaced video signals are first modified by two independent adjustable parameters, each having a different weight on the received signals. A FIFO line buffer is used to delay respectively and alternatively the two modified signals to generate a portion of output signals. The final output interlaced signals are generated by combining the delayed signal from the FIFO line buffer with one of the two modified signals. As a result and for the first time, only one FIFO line buffer is used in such system for producing a converted interlaced signal with minimum visual errors in video signal conversions.

REFERENCES:
patent: 5812203 (1998-09-01), Swan
patent: 5815208 (1998-09-01), Samela et al.
patent: 5822008 (1998-10-01), Inoue et al.
patent: 5892551 (1999-04-01), Uematsu
patent: 5894329 (1999-04-01), Takeda et al.
patent: 5894330 (1999-04-01), Huang et al.
patent: 5896178 (1999-04-01), Inoue

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