Method and architecture for accelerated programming of uniform d

Details Method and architecture for accelerated programming of uniform d Method and architecture for accelerated programming of uniform d

1994-01-03

1995-10-10

Nelms, David C.

Static information storage and retrieval

Floating gate

Data security

36518901, 36523001, G11C 1602

Patent

active

054576512

ABSTRACT:
A method for the programming of a data element in an electrically programmable memory in integrated circuit form comprising a data input/output bus, an address bus, a register for the control of instruction sequencing modes and an enable signal (/OE), said signal enabling the data output bus in an active state. When the control register receives a uniform programming instruction, it sends a uniform programming sequencing mode signal so that an inactive state of the enable signal triggers the programming of the data element at a memory address present in the address bus and so that the active state of the enable signal triggers the stopping of the programming operation. Also disclosed is an electrically programmable memory in integrated circuit form, implementing a method such as this. The disclosure can be applied to electrically programmable memories.

REFERENCES:
Patent Abstracts of Japan, vol. 16, No. 551 (P-1453) 20 Nov. 1992 & JP-A-42 06 094 (Mitsubishi Electric Corp.) 28 Jul. 1992.

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