Boots – shoes – and leggings
Patent
1992-07-31
1994-11-22
Dixon, Joseph L.
Boots, shoes, and leggings
395400, 395775, 395800, 3642318, 3642564, 364260, 3642602, 3642624, G06F 924, G06F 938, G06F 1200, G06F 1500
Patent
active
053676505
ABSTRACT:
A data register file system is provided in a microprocessor having a pipelined execution unit that employs the data register file to store operands and results of its instruction executions. The data register file system includes a plurality of data registers, each of which stores one of the operands and results. A pointer table has a plurality of pointer registers, each storing an address of one of the data registers. A first address generation logic is coupled to the pointer table and the pipelined execution unit for generating a first set of pointer table addresses to access a first group of the pointer registers for the addresses of a first group of the data registers which are required by the execution of a first floating point instruction. The first address generation logic services the first floating point instruction A second address generation logic is coupled to the pointer table and the pipelined execution unit for generating a second set of pointer table addresses to access a second group of the pointer registers for the addresses of a second group of the data registers which are required by the execution of a second instruction. The second address generation logic is provided specifically to facilitate the issue and execution of the second floating point instruction in parallel with the first floating point instruction The second instruction is an exchange instruction that requires an exchange of contents stored in the second group of data registers. A circuit is coupled to the pointer table and the data registers for coupling the addresses of the first group of the data registers to the data registers for accessing the first group of the data registers. A read circuit is coupled to the pointer table for reading the addresses of the second group of the data registers. An exchange circuit is coupled to the read circuit for exchanging the addresses read from the second group of the pointer registers and writing the addresses exchanged back to the second group of the pointer registers. The second instruction is issued and executed in parallel with the first instruction. A method of executing the exchange instruction in parallel with other instructions in the data register file system is also described.
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Sharangpani Harshvardhan P.
Sweedler Jonathan B.
Dixon Joseph L.
Intel Corporation
Whitfield Michael A.
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