Method and apparatuses for managing double data rate in...

Static information storage and retrieval – Hardware for storage elements

Reexamination Certificate

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C365S189020, C365S189050, C365S230060, C365S233100, C365S233130, C365S240000

Reexamination Certificate

active

07995365

ABSTRACT:
Described herein are a method and apparatuses for providing DDR memory access. In one embodiment, an apparatus includes a data storage unit to store and synchronize a plurality of data line signals with a clock signal. The apparatus includes a selector unit that receives the plurality of data line signals and selects two data line signals. The apparatus also includes a double data rate (DDR) output unit that receives the two data line signals from the selector unit and generates a DDR data line signal having a time period substantially one half of a clock time period of the clock signal. The apparatus also includes an input/output (I/O) pad coupled to and locally positioned with respect to the DDR output unit. The data storage unit, the selector unit, and the DDR output unit in combination form an I/O buffer which is locally coupled to the I/O pad.

REFERENCES:
patent: 6212113 (2001-04-01), Maeda
patent: 6549484 (2003-04-01), Morita et al.
patent: 6556486 (2003-04-01), Benzinger et al.
patent: 6603706 (2003-08-01), Nystuen et al.
patent: 6674686 (2004-01-01), Noh et al.
patent: 6717832 (2004-04-01), Johnson et al.
patent: 6972981 (2005-12-01), Ruckerbauer et al.
patent: 7046580 (2006-05-01), Manapat et al.
patent: 7054222 (2006-05-01), Li et al.
patent: 7113417 (2006-09-01), Pochmuller
patent: 7221617 (2007-05-01), Flach et al.
patent: 7227812 (2007-06-01), Li et al.
patent: 7272054 (2007-09-01), Waldrop
patent: 7558151 (2009-07-01), Svoiski
patent: 7688672 (2010-03-01), Best et al.
Hynix Semiconductor, Intel Corporation, Micron Technology, Inc., Phison Electronics Corp., Sony Corporation, Spansion, STMicroelectronics,“Open NAND Flash Interface Specification”, Revision 2.0, Feb. 27, 2008, pp. 174 total.
Wikipedia, the free encyclopedia, “DDR SDRAM”, http://en.wikipedia.org/wiki/DDR—SDRAM, Modified on Dec. 13, 2008, printed on Dec. 15, 2008, pp. 5 total.
JEDEC Electronic Industires Alliance (EIA), “JEDEC Standard, Low Power Double Data Rate (LPDDR) Non-Volatile Memory (NVM) Specification”, JESDxxx, Jan. 2007, JEDEC Solid State Technology Association, pp. 70, plus 2 pages for Preliminary publication of JEDEC Semiconductor Memory Ballot, Ballot No. JCB-07-016, Date of Council Approval, Feb. 2007, pp. 72 total.
IEEE Std 802.11-2007, “IEEE Standard for Information Technology—Telecommunications and information exchange between systems—Local and metropolitan area networks—Specific requirements”, Jun. 12, 2007, pp. 1,233 total.
IEEE Std 802.16.2, “IEEE Recommended Practice for Local and metropolitan area network—Coexistence of Fixed Broadband Wireless Access Systems”, IEEE Computer Society and the IEEE Microwave Theory and Techniques Society, Sponsored by the LANMAN Standards Committee, Mar. 17, 2004, pp. 171 total.

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