Patent
1995-06-02
1997-08-19
Swann, Tod R.
395411, 39542107, G06F 1206
Patent
active
056596952
ABSTRACT:
A method and apparatus for an improving memory access bandwidth that can be used in a digital signal processor (DSP) (500) is accomplished by modifying addresses (302, 304) generated by an address generation unit (AGU) (102) of the DSP (500). Two addresses (302, 304) are generated by the AGU (102). One of the two addresses (302) is used to address two parallel memory blocks (308, 310) in a single memory simultaneously, and the other address (304) is modified by a modulo increment function to produce two additional addresses (404, 406) that also address the parallel memory blocks (308, 310). With such a method and apparatus, four simultaneous memory reads can occur, effectively doubling the memory access bandwidth in the DSP system (500) without modification of the AGU (102) or program controller (510).
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Dao Tan Nhat
Fisher Duncan
Kelley Brian T.
Motorola Inc.
Saunders Keith W.
Swann Tod R.
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