Method and apparatus to reuse existing test patterns to test a s

Details Method and apparatus to reuse existing test patterns to test a s Method and apparatus to reuse existing test patterns to test a s

1994-08-02

1997-04-01

Beausoliel, Jr., Robert W.

Excavating

G06F 1100

Patent

active

056174314

ABSTRACT:
Test vectors are applied to a single integrated circuit containing at least one logic core for which a preexisting test vector set exists. Each test vector ordinarily applied in one cycle to test a core by itself, is converted into a first and second test vector. The first test vector is applied to input pins of the single integrated circuit during a first time period. Test registers connected to the input pins of the integrated circuit are loaded with signal values from the first test vector. The test registers are loaded according to a load signal. The test registers are connected between the input pins and a first set of drivers, the drivers being connected to the logic core under test. The second test vector is applied through the input pins to a second set of drivers during a second time period. A test mode signal is provided from a test interface to control the drivers. The signals stored in the test registers are provided concurrently with the signals applied to the input pins of the integrated circuit during the second time period to the logic core under test through the first and second drivers respectively.

REFERENCES:
patent: 4493045 (1985-01-01), Hughes, Jr.
patent: 4710931 (1987-12-01), Bellay et al.
patent: 4728883 (1988-03-01), Green
patent: 4855670 (1989-08-01), Green
patent: 5115435 (1992-05-01), Langford II et al.
patent: 5329471 (1994-07-01), Swoboda et al.
patent: 5477545 (1995-12-01), Huang

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