Electric power conversion systems – Current conversion – Using semiconductor-type converter
Reexamination Certificate
1999-07-29
2001-04-17
Wong, Peter S. (Department: 2838)
Electric power conversion systems
Current conversion
Using semiconductor-type converter
C363S098000, C363S037000
Reexamination Certificate
active
06219264
ABSTRACT:
BACKGROUND
1. Field
The invention relates to the field of electrical power supply and, more particularly, to electronic rectifier circuits.
2. Background Information
Rectifiers circuits are typically employed in electronic power supplies. Rectifier circuits may accept input signal—often an alternating current (AC) signal—and produce an output signal—often a signal with fewer or different AC characteristics. Typically, diodes may be used to implement rectifier circuits. One limitation of diodes is a characteristic known as “forward voltage drop.” A diode conducting current may exhibit a voltage differential between its input and output terminals, with a corresponding voltage and power loss. The forward voltage drop characteristic can be problematic, especially in low voltage rectifier implementations. Examples of low voltage applications are applications in which the rectifier output voltage signal is less than ten volts. A forward voltage drop for a typical diode may be approximately 0.6 volts. A voltage drop on the order of 0.6 volts may be acceptable in high voltage rectifier applications (for example, for rectifiers with output voltage signals above ten volts). However, such a drop may become a significant loss factor as rectifier output voltages are reduced to the operating levels employed by some modern digital circuits. Circuits employed in modem personal computers, for example, may have output voltage signals at five volts, two volts, or even sub-volt levels. Such circuits may also be designed to provide 20-50 amps of output current or even greater.
Field effect transistors (FETs) may be employed in rectifier circuits instead of diodes. Employing FETs may reduce losses due to forward voltage drop. FETs may exhibit some forward voltage drop, but this drop is typically significantly lower than the forward voltage drop of a diode. An FET circuit may include a source, a drain, and a gate terminal. A bias voltage signal applied to the gate terminal may result in the FET operating as a closed switch. The bias voltage signal may exceed a bias voltage signal threshold level before the FET will operate as a closed switch. In this mode, the FET is considered “on” and may allow a signal (often in the form of current) to propagate between the source and drain terminals. When the bias voltage signal drops below the bias voltage signal threshold level, the FET may operate, approximately, as an open switch. In this mode the FET is considered “off” and may block signal propagation from source to drain terminals. A gate capacitance is typically associated with the gate terminal of an FET. Energy is typically absorbed by the gate capacitance as the gate voltage signal is increased to the bias voltage signal threshold level. This energy may be quantified by the formula:
W=f
*
C
*
V
2
where W is the energy, f is the switching frequency, C is the gate capacitance, and V is the voltage to which the gate capacitor is charged.
Rectifier circuits may comprise a primary stage to which an input voltage signal is applied. Rectifiers may further comprise a secondary stage in which a secondary voltage signal is induced. Induction may occur by way of primary and secondary windings. In schematic diagrams representing such circuits, the direction of the turns on the windings may be indicated by a black dot located proximate to one end of the windings. The design and illustration of rectifiers with primary and secondary stages is well known in the art.
A typical rectifier may employ two FETs in the secondary stage. A first FET conducts a positive cycle of the secondary voltage signal to the output terminals of the rectifier. A second FET conducts a negative cycle of the secondary voltage signal to the output terminals of the rectifier. The resulting output signal of the rectifier may approximate a DC voltage signal. Capacitive effects within the rectifier circuit may further reduce AC components of the output voltage signal. The rectifier may be referred to as a synchronous rectifier when switching of the FETs is accomplished synchronously with the period of the input AC voltage signal, in manners well known in the art. The design and operation of synchronous rectifiers is well known in the art.
A substantial source of rectifier power loss may stem from the “dead-time” of the secondary voltage signal. Dead time is the time during which neither FET is on to conduct the secondary voltage signal to the rectifier output terminals. Dead time is a product of numerous FET characteristics. The gate bias voltage threshold level (the gate bias voltage level which turns the FET on) may have a substantial effect on rectifier dead time. Typical gate bias threshold levels for high-current FETs may range between five and eight volts, although higher or lower gate bias threshold levels are possible as well. As previously described, attaining the gate bias threshold level involves the charging of a gate capacitance, with a corresponding energy consumption. This energy consumption to charge the gate capacitance correlates to a power loss in the rectifier, unless the energy may be recovered when the gate capacitance is discharged. So-called “resonant” circuits recover the power consumed by the gate capacitance, by allowing the gate capacitor to discharge back into the circuit windings, in manners well known in the art.
Some rectifier circuits may employ Schotky diodes to reduce dead time. A Schotky diode may be employed in parallel with the FETs to reduce dead time. Such manners of employing Schotky diodes are well known in the art. The Schotky diodes may add substantial cost to the rectifier circuit. Furthermore, Schotky diodes typically have a threshold voltage level which is exceeded before the diode will conduct a signal from its source terminal to its drain terminal. This threshold voltage level may lead to dead time just as the gate threshold voltage level of FETs may lead to dead time. Furthermore, the Schotky diode may conduct the full current which the FET may conduct during a time when the FET is off and the diode is on, meaning the diode may be rated for high current, making it expensive and possibly large in size. This may mean that large, expensive diodes may be specified for the application. Furthermore, the additional diodes may add capacitance to the rectifier, reducing the frequency response of the secondary stage and increasing power loss.
An ongoing need therefore exists to decrease the dead time when switching FETs, which preserving the resonant character of the switching circuit to reduce power loss.
SUMMARY
In accordance with the present invention, a method includes producing a control voltage signal that exceeds a rated maximum control voltage signal level for a switch, and limiting the control voltage signal applied to the switch to no greater than the rated maximum control voltage signal level.
REFERENCES:
patent: 4519024 (1985-05-01), Federico et al.
patent: 4857822 (1989-08-01), Tabisz et al.
patent: 5014179 (1991-05-01), Latos
patent: 5590032 (1996-12-01), Bowman et al.
Intel Corporation
Mirho Charles A.
Patel Rajnikant B.
Wong Peter S.
LandOfFree
Method and apparatus to reduce rectifier loss does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus to reduce rectifier loss, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus to reduce rectifier loss will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2500304