Electrical computers and digital processing systems: multicomput – Computer-to-computer protocol implementing – Computer-to-computer data transfer regulating
Patent
1996-11-27
1999-11-30
Rinehart, Mark H.
Electrical computers and digital processing systems: multicomput
Computer-to-computer protocol implementing
Computer-to-computer data transfer regulating
710 52, 370516, G06F 1342
Patent
active
059960183
ABSTRACT:
A method and an apparatus for reducing the jitter and end-to-end delay on lines of a packet switching network conveying voice or video digitalized data for one or more connections between a local source and a remote source at a constant bit rate.
The method and apparatus of the invention are for use in a voice or video processor of a voice or video processing server of a network node; the method and the apparatus provide a way of controlling the remote traffic rate from the remote source before accessing the processor without using an external clocking such as the network clock.
The solution proposed by the invention consists in buffering the remote and local traffics to adapt the remote traffic rate to the local traffic rate, which is supposed having a limited jitter, while sequencing of the access of the buffered data to the processor.
REFERENCES:
patent: 4099028 (1978-07-01), Towson, IV
patent: 4270183 (1981-05-01), Robinson et al.
patent: 4748620 (1988-05-01), Adelmann et al.
patent: 5043981 (1991-08-01), Firoozmand et al.
patent: 5140584 (1992-08-01), Suzuki
patent: 5164939 (1992-11-01), Shobatake
patent: 5278825 (1994-01-01), Wallmeier et al.
patent: 5287347 (1994-02-01), Spanke
patent: 5361261 (1994-11-01), Edem et al.
patent: 5425060 (1995-06-01), Roberts et al.
patent: 5497371 (1996-03-01), Ellis et al.
patent: 5519603 (1996-05-01), Allbery, Jr. et al.
patent: 5546389 (1996-08-01), Wippenbeck et al.
patent: 5555264 (1996-09-01), Sallberg et al.
patent: 5563884 (1996-10-01), Fimoff et al.
patent: 5594734 (1997-01-01), Worsley et al.
patent: 5619506 (1997-04-01), Burch et al.
patent: 5664116 (1997-09-01), Gaytan et al.
patent: 5668811 (1997-09-01), Worsley et al.
patent: 5675584 (1997-10-01), Jeong
patent: 5732087 (1998-03-01), Lauer et al.
patent: 5790543 (1998-08-01), Cloutier
patent: 5856975 (1999-01-01), Rostoker et al.
patent: 5862136 (1999-01-01), Irwin
"Constant Bit Rate Services in ATM Networks," NEC Research & Development, 32(1991) Jul., No. 3, Tokyo, JP, by T. Murase, H. Suzuki & T. Takeuchi.
Veil, Len; Wong, Dickson; "Tricky road from legacy LAN to ATM", Electronic Engineering Times, Sep. 18, 1995, n866, p55(1).
Sliter, Tom; "From mainframe to mainstream: SNA integration", STACKS, Miller Freeman Inc., Jan. 1995, v3, n1, p33(9).
Duault Maurice
Galand Claude
Kermarec Francois
Pucci Bernard
International Business Machines - Corporation
McConnell Daniel E.
Rinehart Mark H.
Thompson Marc D
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