Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate
2004-09-30
2008-07-01
Treat, William M (Department: 2181)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
Reexamination Certificate
active
07395415
ABSTRACT:
A method and apparatus for providing a source operand for an instruction to be executed in a processor. Some embodiments may include a register file unit that has registers and a scheduler to schedule instructions. In some embodiments, the scheduler is to asynchronously receive an instruction and a source operand for that instruction, the source operand being received from the register file unit.
REFERENCES:
patent: 5555432 (1996-09-01), Hinton et al.
patent: 5651125 (1997-07-01), Witt et al.
patent: 2003/0200422 (2003-10-01), Hironaka et al.
Crawford John
Hammond Gary
Scafidi Carl
Intel Corporation
Kenyon & Kenyon LLP
Treat William M
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