Method and apparatus to measure internal node timing

Details Method and apparatus to measure internal node timing Method and apparatus to measure internal node timing

1996-06-27

1998-05-19

Wambach, Margaret Rose

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By presence or absence pulse detection

327 3, 327 43, 327263, 327277, 327284, H03K 519

Patent

active

057540632

ABSTRACT:
Internal node timing on an integrated circuit which is supplied with a clock signal from a system clock, the cycle time of which can be varied is measured by connecting a sequential element such as a latch to the node to measured and clocking it with a delayed measurement clock while increasing the clock cycle time. The output of the sequential element is an output pin of said integrated circuit. The measurement clock has the same cycle time as the system clock but has a latching edge delayed, the delay being at least 1.5 times the nominal system clock cycle time when it is desired to make measurement over both the high phase and low phase. The output pin is observed and the clock cycle time at which the sequential element fails to latch the current value determined. In a further embodiment, two sequential elements are used to make two measurements of this type and the difference between the two measurements is used to compute the time delay between the two nodes being measured. One node may be a clock node. By using two such measurements the delay of the measurement clock need not be known. Because frequency is increased instead of decreased in this method and apparatus, it can be used to measure the timing of both static and dynamic circuits without affecting the normal operation of the designed circuit.

REFERENCES:
patent: 5159205 (1992-10-01), Gorecki et al.
patent: 5381416 (1995-01-01), Vartti et al.
patent: 5498983 (1996-03-01), Schoellkopf
patent: 5621360 (1997-04-01), Huang

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