Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Reexamination Certificate
2000-06-19
2002-10-01
Reichard, Dean A. (Department: 2831)
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
C439S091000, C174S255000, C174S260000, C361S760000
Reexamination Certificate
active
06459039
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronic assembly packages, and in particular, to an apparatus and method of making an electronic assembly package wherein two electronic modules, having differing conductive array parameters, are electrically and mechanically interconnected by an interposer structure which spatially transforms such differing conductive array parameters thereby forming the electronic assembly package.
2. Description of Related Art
In surface mount technology, integrated circuits (ICs) have leads, or signal Input/Output (I/O) connections, and Power/ Ground (P/G) connections which are connected to ceramic or organic packages which in turn also have leads extending therefrom. Such IC assemblies include, for example, single chip modules (SCM), wherein one chip is connected to a single chip module, or multi-chip module (MCM), wherein more than one chip is connected to an organic or ceramic package containing multi-layers of thick-film or thin-film circuitry separated by dielectric layers and interconnected by vias. The electrical attachment of the IC to the package, resulting in an IC package, is often referred to as the first level of attachment. In this attachment level, P/G and I/O connections exist on surfaces of both IC dies and first level packages. Such connections terminate in conductive pads or fingers which are used to connect both components using Controlled Collapse Chip Connection (C
4
), or wirebonds. Controlled Collapse Chip Connection is an interconnect technology developed by IBM as an alternative to wire bonding. This technology is generally known as C
4
technology or flip chip packaging. Broadly stated, one or more integrated circuit chips are mounted above a single or multi-layer ceramic substrate and pads on the chip are electrically and mechanically connected to corresponding pads on a substrate by a plurality of electrical connections such as solder bumps. The integrated circuit chips may be assembled in an array such as a 10×10 array on the multi-layer ceramic surface.
The electrical attachment of the IC package to the board is the second level of attachment. In second level attaching, I/O connections exist on surfaces of both IC packages and circuit boards. Such connections terminate in conductive leads, pins, wires, pads, balls, fingers, and any other mating system known in the art, thereby connecting the IC package to a circuit board for receiving, generating or continuing an electrical interconnection. Typically, the second level electrical attachment of two electronic modules using the above connection terminals is achieved by a variety of methods as disclosed in the prior art, such as wire bonding, Pin Grid Arrays (PGAs), Ball Grid Arrays (BGAs), Column Grid Arrays (CGAs), coaxial interconnect devices, elastomeric interconnect devices, and the like. Various such prior art discloses not only connecting the IC package to the board, but also assisting in the absorption of the difference in Coefficient of Thermal Expansion (CTE) between the package and the circuit board. However, even with such attachment means, a large CTE mismatch can still cause failure at various sites in the attachment when the first level packaging is made from a ceramic or metal composite.
Currently, the trend for IC chips is to increase the density and number of I/O connectors on a die, thereby increasing the number of I/O connections at both first and second level attachments. Such trends furthermore result in IC packages and boards with differing conductive connector array parameters such as differing size, shape, pitch, and connector type. Since the board fabrication technology can not easily increase the I/O array density, any increase in I/O count is accommodated by an increase in the dimensions of the I/O connector array required to interconnect to the first level package, whereby the first level package is then used to transform the high density I/O connection of the IC into the low density I/O connection of the board. In parallel, the first level package can accommodate an increase in I/O count by increasing the number of x-y redistribution layers in the package, and by increasing its size to match the increased dimensions of the I/O connection array on the board. When the first level package Coefficient of Thermal Expansion (CTE) is different than the CTE of the second level package, any increase in the size of the first level package size will result in an increased mechanical stress level of the assembly, consequently resulting in decreased product reliability. The above methods of attaching two electronic modules having differing array size, shape, pitch, and the like, with increased I/O count, leads to increased production costs, increased size of the resulting second level attachment, and decreased reliability.
As the trends continue for IC packages having increased density, number of ICs on a package, increased number of I/O connections at the first and second level of attachment, and differing I/O conductive connection array size, shape, pitch, connector type, and the like, the demand continues for improvements in connecting electronic modules in surface mount technology. An ideal first or second level connection scheme is an electronic assembly package that would provide the ability to directly connect two electronic modules having differing I/O conductive connector array parameters such as size, shape, pitch, and connector type, be compatible with the fabrication for a variety of conductive arrays, have a simple mechanical structure such that it can be easily and inexpensively manufactured, have a high processing yield, produce a decrease in the size of the resultant surface mount package, and be consistently reliable. Furthermore, such an electronic assembly package would allow for high density I/O connections, controlled impedance, high signal isolation, and high reliability.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an apparatus and method of fabricating the apparatus for attaching two electronic modules having differing array parameters at a first and/or second level attachment, thereby creating an electronic package.
A further object of the invention is to provide an improved electronic assembly package for first level attachments.
It is yet another object of the present invention to provide an improved electronic assembly package for second level attachments.
Another object of the invention is to provide an improved electronic assembly package having decreased size.
It is yet another object of the present invention to provide an improved electronic assembly package which decreases production costs at the first and/or second level attachment.
Another object of the invention is to provide an improved electronic assembly package without x-y redistribution layers.
Still another object of the invention is to provide a method of making and assembling an improved electronic assembly package having enhanced yield and reliability.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, an electronic package assembly for electrically connecting two electronic modules and method of making the same comprising a first substrate having a first conductive array grid with a first conductive array parameter; a second substrate having a second conductive array grid, said second conductive array grid having differing parameters than said first conductive arrays; an interposer which spatially transforms said differing parameters having a plurality of conductors traversing a thickness of said interposer, said conductors comprising at least a conductive material; and a conductive matrix surrounding said plurality of conductors; and an electronic packag
Bezama Raschid J.
Natarajan Govindarajan
Pasco Robert W.
Oliva Carmelo
Pepper Margaret A.
Reichard Dean A.
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