Boots – shoes – and leggings
Patent
1990-05-14
1993-03-02
Trans, Vincent N.
Boots, shoes, and leggings
364488, 364578, G06F 1560
Patent
active
051915413
ABSTRACT:
The method of the present invention includes steps wherein a circuit designer, using standard computer assisted design (CAD) tools, designs a circuit which may include multi-cycle paths (MCPs). The designer inserts a conceptual circuit element, referred to as a "path breaker" into multi-cycle paths, such that the result is to convert all multi-cycle paths into single cycle paths. The designer then utilizes functional simulation software to edit the circuit design. To the simulator, a path breaker appears to be a latch in which the latch output goes to an unknown state when the input changes, and remains so until the output has been clocked and is equal to the input. Traditional logic synthesis is then performed on the circuit such that a net list is generated which includes the path breakers. Based on the net list, a post processor determines where in the circuit multi-cycle paths exist and generates a net list without path breakers, as well as a list of the multi-cycle paths. The list of multi-cycle paths is provided to a static path analysis program where the locations of the multi-cycle paths denote exceptions. Timing analysis is then performed, and if the circuit is satisfactory, fabrication may be completed using the net list without the conceptual path breakers.
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"MIS: A Multiple-Level Logic Optimization System" by Brayton et al., IEEE Trans. on Computer-Aided Design, vol. CAD-6, No. 6, Nov. 1987, pp. 1062-1081.
"Switch-Level Delay Models for Digital MOS VLSI" by J. K. Ousterhout, IEEE 21st Design Automation Conf. 1984, pp. 542-548.
"Timing Analysis for nMOS VLSI" by N. P. Jouppi, IEEE 20th Design Automation Conf. 1983, pp. 411-418.
Bucher Tim
Kuang Ser-hou
Landman Howard
Sun Microsystems Inc.
Trans Vincent N.
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