Excavating
Patent
1992-10-30
1995-09-19
Canney, Vincent
Excavating
371 55, 371 28, G06F 1100
Patent
active
054523117
ABSTRACT:
Apparatus for controlling a length of a period during which the output circuitry of a memory array waits before latching the output data including apparatus for detecting the presence of an error in data read from an memory array, apparatus for providing a first value to determine a wait period, apparatus responsive to the detection of an error for providing a second value, apparatus responsive to the first value for generating a signal to latch a data output from the memory array after a first period and responsive to the second value for generating a signal to latch a data output from the memory array after a second period.
REFERENCES:
patent: 4642759 (1987-02-01), Foster
patent: 4644494 (1987-02-01), Muller
patent: 4763305 (1988-08-01), Kuo
patent: 4802117 (1989-01-01), Chrosny et al.
patent: 4896262 (1990-01-01), Wayama et al.
patent: 4958315 (1990-09-01), Balch
patent: 5012425 (1991-04-01), Brown
patent: 5067128 (1991-11-01), Nakame
patent: 5070474 (1991-12-01), Tuma et al.
patent: 5077737 (1991-12-01), Leger et al.
patent: 5131089 (1992-07-01), Cole
patent: 5200959 (1993-04-01), Gross et al.
patent: 5268906 (1993-12-01), Free
Solid--State Mass Storage Arrives, Product Feature, Memory Card Systems & Design, Jul./Aug. 1992.
Mielke Neal
Wells Steven
Canney Vincent
Intel Corporation
LandOfFree
Method and apparatus to improve read reliability in semiconducto does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus to improve read reliability in semiconducto, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus to improve read reliability in semiconducto will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1834445