Method and apparatus to expand an on chip FIFO into local memory

Multiplex communications – Data flow congestion prevention or control – Flow control of data transmission through a network

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370412, H04L 1228, H04J 116

Patent

active

060785659

ABSTRACT:
A relatively small FIFO queue is located on a semiconductor chip receiving and transmitting data in a computer system, typically a computer network. The FIFO queue has additional storage capability in the form of an expansion into the local memory of the computer system. The front and back ends of the FIFO, which are involved in receiving and transmitting data, are implemented on the chip. The FIFO expands into the space provided in the local memory only when the on-chip portion of the FIFO is full. The middle portion of the FIFO resides in expansion in the local memory. The local memory is accessed only in bursts of multiple credits, both for read transactions and for write transactions.

REFERENCES:
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patent: 5572522 (1996-11-01), Calamvokis et al.
patent: 5633867 (1997-05-01), Ben-nun et al.
patent: 5649110 (1997-07-01), Ben-nun et al.

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