Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-02-16
2003-11-18
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06650136
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to design for test improvements, and specifically to a method and apparatus for increased ability to observe and control logic nodes located between input/output buffers and a first set of flops within a core of the integrated device.
2. Description of the Related Art
As the technology for manufacturing integrated circuits advances, more logic functions are included in a single integrated circuit device. Modern integrated circuit (IC) devices include large numbers of gates on a single semiconductor chip, with these gates interconnected so as to perform multiple and complex functions. The fabrication of an IC incorporating such Very Large Scale Integration (VLSI) must be error free, as a manufacturing defect may prevent the IC from performing all of the functions that an IC is designed to perform. Such demands require verification of the design of the IC and also various types of electrical testing after the IC is manufactured.
However, as the complexity of the IC increases, so does the cost and complexity of verifying and electrically testing each of the devices in the IC. Electrical testing ensures that each node in a VLSI circuit functions properly. Therefore, each node needs to individually, and in conjunction with the other node in the IC, function properly in all possible combinations of operations. Typically, electrical testing is performed by automated testing equipment (ATE) that employs test vectors to perform the desired tests. A test vector describes the desired test input (or signals), associated clock pulse (or pulses), and expected test output (or signals) for every package pin during a period of time, often in an attempt to “test” a particular node. For complex circuitry, this may involve a large number of test vectors and, accordingly, a long test time.
One way to address this problem is through design for test (DFT). The key concepts in DFT are controllability and observability. Controllability is the ability to set and reset the state of every node in the IC. Observability is the ability to observe either directly or indirectly the state of any node in the IC. The purpose of DFT is to increase the ability to control and observe internal and external nodes from external inputs/outputs.
DFT methods utilize various test circuits. One type of test circuit is a scan path or a scan loop in the logic circuit. A scan path or scan loop comprises of a chain of synchronously clocked master/slave latches (or registers), each of which is connected to a particular node in the logic circuit. Typical scan circuit designs involve two or more separate scan paths or scan loops. The scan latches can be loaded with a serial data stream of scan vectors that set the logic circuit nodes to a predetermined state. The logic circuit then can be operated in normal fashion and the result of the operation is stored in its respective latch. A scan out operation serially unloads the contents of the latches and the result of the test operation at the associated nodes is analyzed for improper node operation.
The load and scan out operations are performed via a test port. One example of a test port is a defined by the Institute of Electrical and Electronic Engineers(IEEE) is a Joint Test Action Group (JTAG) test protocols set forth in IEEE standard 1149.1. In such a system, a JTAG test device is connected to a pair of ICs or to a single IC. The JTAG device generates test commands for testing the ICs. Input and output of JTAG test commands is achieved through a set of JTAG-dedicated pins provided on each IC to be tested. Typically, the JTAG test device is employed to perform scan test. General information regarding JTAG and scan test strategies and implementations may be found in “Boundary-Scan Test, A Practical Approach”, by Harry Bleeker, Peter Van Den Eijnden and Frans de Jong, Kluwer Academic publishers 1993.
Testing costs and complexity increase dramatically because of the increasing number of functional pins on the integrated devices. One solution for reducing test costs is to use test equipment with a capability to only test a limited number of pins with a limited number of test channels. However, testing and fault coverage suffers because of the inability to control and observe various logic nodes within the integrated device due to the lack of dedicated tester channels. Specifically, input/output buffers require a large number of tester channels and suffer from a lack of fault coverage because of a lack of observability and controllability for logic coupled to the input/output buffers.
REFERENCES:
patent: 5528610 (1996-06-01), Edler et al.
patent: 5631911 (1997-05-01), Whetsel, Jr.
patent: 5671234 (1997-09-01), Phillips et al.
patent: 5960008 (1999-09-01), Osawa et al.
Babella Anthony
Udawatta Kapila B.
Uddin Razi
Blakely , Sokoloff, Taylor & Zafman LLP
Cuneo Kamand
Intel Corporation
Tang Minh N.
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