Electric power conversion systems – Current conversion – Including d.c.-a.c.-d.c. converter
Reexamination Certificate
2001-04-09
2002-07-09
Nguyen, Matthew (Department: 2838)
Electric power conversion systems
Current conversion
Including d.c.-a.c.-d.c. converter
C363S021050
Reexamination Certificate
active
06418039
ABSTRACT:
TECHNICAL FIELD
This invention is directed toward switched mode power supplies, and more particularly, to a method and device for controlling synchronous rectifiers used within a switched mode power supply.
BACKGROUND OF THE INVENTION
In the power conversion area, especially in low DC output voltage converters, the utilization of MOSFETs as rectifiers is a technique increasingly used for the beneficial effect on efficiency due to the low conduction losses on these devices.
The way the synchronous rectifiers (SRs) are controlled is fundamental for the correct operation of the circuit. Proper techniques have therefore to be used to drive these SRs according to the law of the diode that the SR is meant to replace. This driving signal is derived from the main PWM control signal, which determines the different states of the switch mode circuit and therefore the operating conditions for the diodes of the circuit.
The way the driving signal can be derived from the main PWM signal to properly control SRs depends on the kind of topology used, and on the presence of voltage isolation in that topology. In a non-isolated switched mode power supply topology, the synchronous rectifier control circuit can get the information about the switching transitions (turn-off and turn-on) of the main switch from the main control circuit in a very simple way.
In isolated topologies with a primary side control, the absence of a PWM controlling signal on the secondary side of the isolation barrier makes the generation of the proper control signals for the SRs even more difficult.
If the equivalent diode law is not respected, the well known phenomena of cross conduction and shoot-through between switches will occur, as described in detail below. In all of these circumstances, one of the switches is forced to conduct in the first quadrant, opposite to its useful sense of conduction as a diode. Therefore, switching losses can become predominant, wasting most of the benefits introduced by the reduction of conduction losses by the rectifiers, or can even prevent proper operation of the circuit.
The required timing of the driving signal for the synchronous rectifier is shown in
FIG. 2
, having to a general switch mode topology configuration with one switch and only one diode, where the conduction times possible for switch and diode are complementary.
The dead time intervals shown in that figure prevent contemporary cross-conduction of the main switch and the SR, but they must be reduced to the lowest possible time value to minimize SR parasitic diode conduction times, and the consequent lost of efficiency.
In fact, an important issue in control of MOSFET SRs is related to the body-diode behavior. Physical MOSFETs used as SRs show, in fact, bad characteristics in terms of a parasitic diode, whose operation is involved at least during transitions between different states.
The operation of the body-diode is dependent on the timing of the driving signals, and in particular by the turn-off instant of the SR with respect to the time interval in which the diode (which has been replaced by a MOSFET SR) is supposed to be conducting.
A too early turn-off of the SR will cause an increase of conduction losses due to the body-diode drop which will therefore conduct all the current. The switching losses caused by the reverse recovery current of the body-diode will be dependent by the carried current at the instant in which the voltage between anode and cathode reverses, becoming negative.
In isolated topologies, if the main PWM is located on the secondary side, the task of driving synchronous rectifiers can be easily solved. In fact, because the PWM signal is available on the secondary side, it can be used to generate the driving signal for the SRs. Delays can be added to the PWM signal to compensate the propagation delays which are suffered by the driving signal transferred to the primary side through some coupling device. The required timing for this kind of operation is shown in
FIG. 3
, in the more general case of two complementary signals on the secondary side. Even in this application, dead times among driving signals are necessary to prevent eventual cross conduction between the SRs and between SRs and the main MOSFET.
However, secondary side control configuration shows several system disadvantages, such as requirement of an auxiliary power supply for startup of the converter, requirement of a crossing-isolation circuit able to transfer the PWM control driving signal to primary switches, and difficulties to transfer the information about the primary switch current to the PWM controller in current mode control loops. Therefore, the use of PWM control on the primary side is mandatory to realize switched mode power supplies (SMPS) with top performances in terms of high efficiency, small dimensions and low cost.
In isolated topologies, if the main PWM control circuit is on the primary side, its signal cannot be available on the secondary side in a simple, effective and cheap way. This information can be however derived on the secondary side from the output of the isolation transformer. In this case, however, it is noted that the synchronizing signal withdrawn at the output of isolation transformer is the effect of primary main switch commutations. This signal, in fact, shows a behavior similar to the main PWM signal, at least in continuous conduction mode (CCM), but it is affected by the parasitic elements of the circuit. In addition, if the CCM working condition is not respected, it may also present some oscillations during part of the signal, which can determine false driving information. Therefore, the control technique meant to provide SR driving signals has to be able to prevent eventual rising of wrong operative conditions derived by any timing effects on the synchronization of the signal available on the secondary PWM synchronization signal with respect to the primary PWM signal.
Using the output of the isolation transformer as the PWM synchronization signal, a very simple way to make MOSFETs operate as rectifiers in isolated topologies based on forward topology is a technique called “self-driven synchronous rectification.”
A very basic example of this technique, which has been developed in many different proprietary versions, is provided in the single ended forward topology of FIG.
4
A.
If the gate of MOSFET
3
is connected to node
5
, and the gate of MOSFET
4
is connected to node
6
, the two MOSFETs are driven correctly, according to the equivalent diodes law. Unfortunately, this technique suffers a very serious inconvenience. As it can be observed in the related timing diagram of
FIG. 4B
, the driving signal is dependent on the way in which the main transformer is demagnetized during a magnetic reset. As a consequence, the time in which the body diodes of the MOSFET
4
is forced to conduct can be very large, due to the fact that the driving signal for the gate is missing. This fact damages the main benefits introduced by synchronous rectification, restricting the use of this method for driving SRs only in combination with some particular, and proprietary magnetic reset techniques.
In addition, this technique is hard to implement when the primary input voltage has a very wide range of variation. Common factors are limited to about 2:1, because it is difficult to always provide a driving signal value compatible with the appropriate ranges of the gates.
Therefore, in isolated topologies with primary side control, the most proper approach to drive SRs requires a control circuit able to handle the synchronization signal (clock) separate from the output of the isolation transformer, and to solve any other problem regarding the timing of the driving signals (Out
1
, Out
2
) with respect to the clock input. In
FIG. 5
, the general Clock signal at a fixed switching frequency, with primary switch On and Off time intervals is shown.
The control circuit has to deal with proper timing generation of the SR driving signal from the clock signal input. According to
FIG. 2
, and as already explained, proper deadtime
Cala' Ignazio
Lentini Franco
Librizzi Fabrizio
Scalia Pietro
Iannucci Robert
Jorgenson Lisa K.
Nguyen Matthew
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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