Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Integrated structure
Reexamination Certificate
1999-11-24
2003-09-23
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Integrated structure
C327S565000
Reexamination Certificate
active
06624690
ABSTRACT:
BACKGROUND
1. Field
The invention relates to the field of electrical signals and more particularly, to the reflection of electrical signals along a circuit path.
2. Background Information
Electrical circuits often have their operation driven by a signal which is known as a “clock” signal (which may also be called a “trigger” signal). The trigger signal typically takes the form of a pulse which rises from a first predetermined voltage level (typically called “low”) to a second predetermined voltage level (typically called “high”). Of course, the designation of which voltage level constitutes a “low” or “high” is merely a matter of convention. Circuits which receive a trigger signal typically have their operation triggered when the trigger signal crosses a “trigger” level. The trigger level is a voltage level between the first predetermined level and the second predetermined level. As the voltage of the trigger signal rises between these levels, it crosses the trigger level with the result that the circuit receiving the trigger signal may perform an operation. For example, the well known latching circuit may read in and store a signal on a data input terminal where the trigger signal crosses the trigger level. When this occurs, the latch circuit is said to have been “triggered” or “clocked”. Of course, a circuit's operation may also be triggered by the transition of the trigger signal from the higher predetermined voltage level to the lower predetermined voltage level. The transition of a trigger signal from low to high voltage levels may be referred to as a “rising” edge of a trigger signal. Likewise, the transition from high to low voltage levels of a trigger signal may be referred to as the “falling” edge.
Some circuits are capable of performing multiple operations, with some operations triggered on a rising edge and others triggered on the falling edge of a trigger signal. For example, a memory circuit may write (e.g. store) signals on its data input terminals and may read (e.g. output) signals stored in the memory to its data output terminals. The memory write operation may be triggered on the rising edge of a trigger signal and the memory read operation may be triggered on the falling edge of the trigger signal. Some memory circuits may be capable of performing a write operation and a read operation each triggered by the rising and falling edges of the same trigger signal.
In some situations it may be desirable to substantially delay the triggering of the operation on the rising edge, without causing substantial delay to the triggering of the operation on the falling edge, or vice versa. For example, it may be desirable to delay the triggering of a memory write operation on the rising edge of a clock pulse, without delaying the triggering of a memory read operation on the falling edge of the same trigger signal. This may be desirable when the signals on the data input terminals are not available at the point in time when the rising edge of the trigger signal triggers a memory write operation. The circuits which read data signals from the data output terminals of the memory may be configured to receive the data signals shortly after the same trigger signal triggers a memory read operation. Thus it may not be acceptable to simply delay the entire trigger signal to delay the rising edge, because by delaying the entire trigger signal, both the rising and falling edges are delayed, which interferes with the memory read operation. The circuit reading data signals from the memory would be forced to incur delays to accommodate the delays in the memory write operation.
One solution to this problem is to narrow the trigger signal so that the falling edge occurs sooner after the rising edge. By narrowing the trigger signal, the time at which the rising edge occurs may be delayed without altering the time in which the falling edge occurs. This approach may not be feasible in applications where the trigger signal is distributed to multiple circuits, some of which are adapted to expect the rising edge to occur at a predetermined point in time and at least one circuit adapted to expect the rising edge to be delayed. In this situation, simply adapting the trigger signal generator to produce a narrower trigger signal may be undesirable because the operation of some of the circuits receiving the trigger signal may be adversely affected. Those skilled in the art will recognize that the same situation could arise in situations where the timing of the rising edge is to be left unchanged, but where the falling edge needs to occur sooner in time.
Thus, there exists a continuing need for a mechanism by which the timing of one edge of a signal received by circuit may be adjusted without substantially changing the timing of the other edge of the signal, and without altering the timing of the signal edges to other circuits which receive the signal.
SUMMARY
An apparatus includes a circuit and a signal source to supply a trigger signal to the circuit. The signal source is adapted to supply the trigger signal such that a reflection of the trigger signal delays the time at which the circuit is triggered.
REFERENCES:
patent: 5125009 (1992-06-01), DeVilbiss
patent: 5532500 (1996-07-01), Okamura et al.
patent: 6065129 (2000-05-01), Sakamoto et al.
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