Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
2007-01-02
2007-01-02
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S172000
Reexamination Certificate
active
10601047
ABSTRACT:
Some microprocessors are designed such that the microprocessor core clock has a duty cycle of approximately fifty percent. When a clock signal propagates across power domains the clock signal pulse shape will change. The rising edges and falling edges of the clock signal will become asymmetrical (e.g., the duty cycle is no longer fifty percent). According to embodiments of the present invention, a parallel divide function is applied to a clock signal having a frequency f and its complement. The resulting four signals (i.e., f/2, its complement, f/2 at ninety degrees out of phase from f/2 and its complement) are applied to an XOR gate that combines them to generate a clock signal that has a duty cycle of approximately fifty percent and a frequency f, which is the same as the input clock signal.
REFERENCES:
patent: 6737927 (2004-05-01), Hsieh
Young, I. A., “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors,”IEEE Journal of Solid-State Circuits, vol. 27, No. 11, (Nov. 1992), pp. 1599-1606.
Wong, K. L. et al., “Cascaded PLL Design for a 90nm High Performance Microprocessor,” Intel Corporation, Hillsboro, Oregon.
Law Hon-Mo Raymond
Parker Rachael J.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Le Dinh T.
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