Method and apparatus to achieve a process, temperature and...

Oscillators – With frequency calibration or testing

Reexamination Certificate

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C331S011000, C331S014000, C331S016000, C331S025000

Reexamination Certificate

active

07095287

ABSTRACT:
Several open-loop calibration techniques for phase-locked-loop circuits (PLL) that provide a process, temperature and divider modulus independence for the loop bandwidth and damping factor are disclosed. Two categories of open-loop techniques are presented. The first method uses only a single measurement of the output frequency from the oscillator and adjusts a single PLL loop element that performs a simultaneous calibration of both the loop bandwidth and damping factor. The output frequency is measured for a given value of the oscillator control signal and the charge-pump current is adjusted such that it cancels the process variation of the oscillator gain. The second method uses two separate and orthogonal calibration steps, both of them based on the measurement of the output frequency from the oscillator when a known excitation is applied to the open loop signal path. In the first step the loop bandwidth is calibrated by adjusting the charge-pump current based on the measurement of the forward path gain when applying a constant phase shift between the two clocks that go to the phase frequency detector, while the integral path is hold to a constant value. During the second step the damping factor is calibrated by adjusting the value of the integral loop filter capacitor based on the measurement of the oscillator output frequency when excited with a voltage proportional with the integral capacitor value, while the proportional control component is zeroed-out.

REFERENCES:
patent: 2003/0203720 (2003-10-01), Oosawa et al.
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Maneatis et al., “Self-Biased, High-Bandwidth, Low-Jitter 1-to-4096 Multiplier Clock-Generator PLL”, IEEE Journal Of Solid-State Circuits, vol. 38, No. 11, Nov. 2003, pps. 1795-1803.
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Maxim, “A Low Voltage, 10-2550MHz, O.15μ CMOS, Process And Divider Modulus Independent PLL Using Zero-VT MOSFETs”, IEEE, 2003, pp. 105-108.
Payne et al, “A 150-MHz Translinear Phase-Locked Loop”, IEEE Transactions On Circuits And Systems-II: Analog And Digital Signal Processing, vol. 45, No. 9, Sep. 1998, pp. 1220-1231.
Maxim et al., “A Low-Jitter 125-1250-MHz Process-Independent And Ripple-Poleless 0.18μm CMOS PLL Based On A Sample-Reset Loop Filter”, IEEE Journal Of Solid-State Circuits, vol. 36, No. 11, Nov. 2001, pp. 1673-1683.

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