Oscillators – Automatic frequency stabilization using a phase or frequency... – Tuning compensation
Reexamination Certificate
2001-09-18
2004-08-31
Tokar, Michael (Department: 2819)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Tuning compensation
C377S047000
Reexamination Certificate
active
06784751
ABSTRACT:
TECHNICAL FIELD
These teachings relate generally to signal generation circuits, such as local oscillator (LO) circuits, and more particularly relate to integer N and fractional N phase locked loop (PLL) circuitry and to prescaler circuitry employed in PLLs.
BACKGROUND
In a PLL application the noise generated by a prescaler can be particularly troublesome. The prescaler is typically implemented as a chain of frequency divider circuits (e.g., flip/flops and/or counters) and functions to scale, i.e., pre-scale, an input clock signal to some desired frequency. The frequency-scaled signal may be used in the PLL closed loop path between a voltage controlled oscillator (VCO) and the input of a phase comparator. In these types of frequency divider chains the last divider(s) typical generate the predominant noise component. The noise arises primarily from the asynchronously running frequency dividers and from the resulting temporal ambiguity or jitter in the edges of the prescaler output signal. The presence of the jitter in the output signal of the prescaler is manifested as circuit noise in downstream circuitry. A component of the noise can also arise from spurious signals generated by the prescaler itself, such as when the prescaler modulus is changed when using a phase rotation or phase switching PLL topology. The modulus of the prescaler (e.g., modulus or mod N) specifies the ratio of the input frequency to the output frequency (e.g., a mod 64 prescaler divides the input signal by 64 to produce the output signal.) This is an example of an integer modulus prescaler. However, non-integer or fractional modulus prescalers may also be employed.
In an integrated circuit design one needs a certain signal level to overcome signals (noise) found in the substrate and generated elsewhere. In high speed emitter-coupled logic (ECL) designs, typically used for high frequency circuits, the logical levels are made very small (typically 200-500 mV), and are generated by currents passing through a resistor. If the signal swing is too small then there are basically two options available to the designer: (a) increase the current, or (b) increase the resistor value. However, an increased resistor value results in increased thermal noise from the resistance. Thus, for low noise applications it is preferable to use a higher current and smaller resistors.
In an effort to reduce the prescaler noise it has been known to increase the current to the last divider(s) in the frequency divider chain. However, this approach is less than optimum when the prescaler forms a part of a PLL that in turn is incorporated into a battery powered portable device like a mobile communicator or mobile station, such as a cellular telephone. For example, the PLL may form a part of a frequency synthesizer that provides a tunable frequency local oscillator signal to one of an Inphase/Quadrature (I/Q) demodulator in an RF receiver chain or an I/Q modulator in an RF transmitter chain. In some applications a common frequency synthesizer and PLL combination may provide a single tunable frequency to both the IQ demodulator and to the IQ modulator. In some applications the receiver chain may be a direct conversion type of receiver wherein the input (received) RF signal is downconverted directly to a base band signal.
In any of these embodiments it can be appreciated that it is desirable that the output of the frequency synthesizer be noise-free, or substantially noise free, and furthermore that the reduction in the noise be accomplished using as little operating (battery) power as is possible.
SUMMARY OF THE PREFERRED EMBODIMENTS
The foregoing and other problems are overcome, and other advantages are realized, in accordance with the presently preferred embodiments of these teachings.
In accordance with the teachings of this invention a resampling technique is used to reduce the noise and improve the signal quality in the output of the prescaler. The resampling of the output of, by example, a last frequency divider stage is accomplished using at least one flip/flop (FF) (e.g., a D-type FF) that is clocked by a signal obtained from the input of the prescaler. This reduces or eliminates the edge jitter, as well as the effect of spurious signals generated by the prescaler. These teachings can be used in integer N PLLs and in fractional N PLLs, as well as in single and programmable dual or multi-modulus prescalers.
An advantage of the use of these teachings is that the current consumption of the prescaler frequency dividers need not be increased in an effort to reduce the prescaler noise. It is assumed that the additional current consumption that is required by the use of the additional F/F or F/Fs does not exceed the amount of additional current that would need to be supplied to the prescaler in order to reduce the noise by an equivalent amount.
In one aspect this invention provides a phase locked loop having a phase comparator that generates an output signal that is used to drive a voltage controlled oscillator, and a modulus N prescaler circuit coupled to an output of the voltage controlled oscillator. The prescaler circuit has an input node for coupling to the voltage controlled oscillator for receiving an input signal having a characteristic frequency that is to be divided by N, an output node for outputting a frequency divided signal that is coupled to the phase comparator, and a plurality of divider stages coupled between the input node and the output node for dividing the input signal by N. The prescaler circuit further includes at least one resampling stage coupled to an output of at least one of the divider stages for receiving an output signal therefrom and for synchronizing edges of the output signal to edges of the input signal, thereby reducing the amount of temporal ambiguity in the occurrences of the edges of the output signal. The value of N may be programmable. The at least one resampling stage may be implemented using a D-type flip-flop that is clocked with the input signal.
Also disclosed is a method for reducing the power consumption in a frequency source of a mobile station. The method includes operating a phase locked loop as part of the frequency source to generate a signal having a desired frequency. The step of operating the phase locked loop includes a step of dividing a frequency of an output signal of a voltage controlled oscillator by a predetermined amount and resampling the frequency divided signal using the output signal of the voltage controlled oscillator to reduce jitter in the frequency divided signal, without increasing the current consumption of frequency divider circuits that comprise the phase locked loop. The step of resampling operates a modulus N prescaler circuit that is coupled to the output of the voltage controlled oscillator. The prescaler circuit has the input node for coupling to the output of the voltage controlled oscillator for receiving the input signal having the characteristic frequency to be divided by N, an output node for outputting the frequency divided signal that is coupled to the phase comparator of the phase locked loop, and a plurality of the frequency divider circuits coupled between the input node and the output node for dividing the input signal by N. The step of resampling is accomplished in a resampling stage coupled to an output of at least one of the frequency divider circuits for receiving an output signal therefrom and for synchronizing edges of the output signal to edges of the input signal, thereby reducing jitter in the output signal.
These teachings also provide a method for operating a phase locked loop as part of a frequency source to generate a signal having a desired frequency. The method includes operating a multi-modulus prescaler function of the phase locked loop to divide a frequency of an output signal of an oscillator by a predetermined amount, and resampling the frequency divided signal using the output signal of the oscillator to equalize a delay added in different modes of the multi-modulus prescaler function. Advantageously, the delay is equalized w
Salmi Mika
Svard Mikael
Harrington & Smith ,LLP
Nguyen Linh V
Nokia Corporation
Tokar Michael
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