Patent
1996-02-12
1997-10-14
Robertson, David L.
G06F 1338
Patent
active
056780095
ABSTRACT:
A method and apparatus for transferring control of a memory bus, providing access to a memory array, from a controller having control of the memory bus to a controller desiring control of the memory bus are described. The method requires generating an access request directed to the controller having control from the controller desiring control, which is then detected by the controller desiring control. A determination is made as to whether the memory bus is being used, by the controller having control, by sampling the row address strobe (#RAS) line. A fast bus transfer sequence is initiated if the memory bus is not in use, the fast transfer sequence transferring control of the memory bus to the controller desiring control after a first time period. Alternatively, a slow bus transfer sequence is initiated, when the memory bus use is over, if the memory bus is in use. The slow transfer sequence transfers control to the controller desiring control after a second time period, which is longer than the first time period and which includes a precharge period not included in the first time period. Thus when the fast transfer sequence is performed, unnecessary precharging of memory selection circuitry is avoided.
REFERENCES:
patent: 5448703 (1995-09-01), Amini et al.
patent: 5517626 (1996-05-01), Archer et al.
Bains Kuljit S.
Crocker Kenneth M.
Freker David E.
Intel Corporation
Robertson David L.
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