Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
2011-04-05
2011-04-05
Chan, Jason (Department: 2622)
Television
Camera, system and detail
Solid-state image sensor
C348S302000, C348S304000
Reexamination Certificate
active
07920190
ABSTRACT:
An imaging apparatus and a method using column processing circuits arranged in multiple rows for processing pixels in a pixel array.
REFERENCES:
patent: 6137432 (2000-10-01), Xiao
patent: 6452149 (2002-09-01), Yamashita et al.
patent: 6545624 (2003-04-01), Lee et al.
patent: 6757018 (2004-06-01), Fowler
patent: 6885396 (2005-04-01), Panicacci et al.
patent: 6943838 (2005-09-01), Fossum et al.
patent: 6984816 (2006-01-01), Holm et al.
patent: 7068319 (2006-06-01), Barna et al.
patent: 7565033 (2009-07-01), Hanson et al.
patent: 7623173 (2009-11-01), Nitta et al.
patent: 2004/0041931 (2004-03-01), Tu et al.
patent: 2005/0134714 (2005-06-01), Carlson et al.
patent: 2005/0195304 (2005-09-01), Nitta et al.
patent: 2005/0195645 (2005-09-01), Panicacci et al.
patent: 2005/0253942 (2005-11-01), Muramatsu et al.
patent: 2006/0119903 (2006-06-01), Chiba et al.
patent: 2003259234 (2003-09-01), None
Forchheimer R et al., “Single-Chip Image SEnsors With a Digital Processor Array”, Apr. 1, 1993, Journal of VLSI Signal Processing, vol. 5 No. 2/03, pp. 121-131.
International Search Report and Written Opinion dated Dec. 19, 2008 issued in Application No. PCT/US2008/078910.
Tabet, Muahel et al., “CMOS image sensor camera with focal plane edge detection,” Electrial and Computer Engineering, vol. 2, pp. 1129-1133, May 13, 2001.
Kleinfelder, Stuart et al., “A 10000 frames/s CMOS digital pixel sensor,” IEEE Journal of Solid-State Circuits, vol. 36, No. 12, pp. 2049-2059, Dec. 2001.
Forchheimer, Robert, “Single-chip image sensors with a digital processor array,” Journal of VLSI Signal Processing, vol. 5, Nos. 2/3, pp. 121-131, Apr. 1993.
El Gamal, Abbas et al., “CMOS image sensors,” IEEE Circuits & Devices Magazine, vol. 21, No. 3, pp. 6-20, May 2005.
Burns, J. et al., “Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip,” IEEE International Solid-State Circuits Conference, pp. 268-269, p. 453, Feb. 2001.
Mendis, Sunetra K. et al., “CMOS active pixel image sensors for highly integrated imaging systems,” IEEE Journal of Solid-State Circuits, vol. 32, No. 2, pp. 187-197, Feb. 1997.
H. Yamashita and H. Sodini; A 128x128 CMOS imager with 4x128 bit-serial column-parallel PE array; Solid-State Circuits Conference, 2001, Digest of Technical Papers; 2001; pp. 96-97, 436; !SSCC, IEEE International; ISBN 0-7803-6608-5; San Francisco, California, U.S.A.
Abbas El Gamal, David Yang, and Boyd Fowler Information Systems Laboratory, Stanford University; Pixel Level Processing—Why, What, and How?; IS&T/SPIE Conference on Sensors, Cameras, and Applications for Digital Photography, San Jose, California; Jan. 1999; pp. 1-3; SPIE vol. 3650; No. 0277-786X/99; Information Systems Laboratory, Stanford University, Stanford, California, U.S.A.
Apr. 22, 2010 International Preliminary Report on Patentability and Written Opinion (7 pages).
Martinussen Tore
Moholt Jorgen
Aptina Imaging Corporation
Chan Jason
Prabhakher Pritham
LandOfFree
Method and apparatus providing column parallel architecture... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus providing column parallel architecture..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus providing column parallel architecture... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2722039