Patent
1996-11-07
1999-03-30
Lall, Parshotam S.
395381, G06F 938
Patent
active
058899758
ABSTRACT:
A processor core suitable for use with a wide variety of instruction fetch units. The processor core contains a plurality of pipe stages including an instruction pointer generation stage and a decode stage. The core bundles all control necessary for downstream pipeline operation with an instruction address in a first stage. The bundle is transmitted outside the core to the instruction fetch unit. The instruction fetch unit fetches the instruction and adds it to the bundle, before forwarding the bundle as modified back within the core and down the pipeline. In this way, an external pipe stage is introduced providing a connection between discontinuous pipe stages in the core. Additionally, by bundling the control signals and address information in a single bundle that traverses the external pipe stage as a group, synchronization concerns are reduced or eliminated.
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Adelmeyer Thomas
Heeb Jay
Meyer Paul G.
O'Connor Dennis
Strazdus Stephen
Intel Corporation
Lall Parshotam S.
Vu Viet
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