Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-11-27
2003-07-01
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C324S765010
Reexamination Certificate
active
06586265
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus of tool matching for a semiconductor manufacturing process.
2. Description of the Prior Art
One of the critical factors for success of mass production is yield, defined as the proportion of the number of qualified products to the total number of products. In semiconductor manufacturing, the products are wafers or chips, and the corresponding wafer yield and chip yield are significant. Improvement of the wafer and chip yield reduces the cost and increases production efficiency since most of the wafers or chips are qualified and few are wasted. Therefore, manufacturing engineers are dedicated to the improvement of yield.
Conventionally, for improvement of the yield, engineers choose, from the available tools for each one step or operation in the manufacturing process of a product, the one in the best condition. However, the combination of the selected tools is only a possibly but not absolutely optimized path since the tools are selected individually for each step and correlation between the tools is ignored.
SUMMARY OF THE INVENTION
Therefore, the object of the present invention is to provide a method and apparatus of tool matching for a semiconductor manufacturing process, wherein the correlation between the tools is taken into account so that an absolutely optimized path is provided.
The present invention provides a method of tool matching for a semiconductor manufacturing process having a first and second path completed by serial combinations of tools for processing of wafers. The method comprises the steps of providing a target value, obtaining a first and second test result of the wafers processed through the first and second path respectively, calculating differences between the first and second test result and the target value to obtain a first and second estimate respectively, and selecting one of the first and second path according to the estimates.
The present invention also provides a method of tool matching for a semiconductor manufacturing process having a plurality of paths completed by serial combinations of tools for processing of lots of wafers. The method comprises the steps of providing a target value T, obtaining groups of test results of lots of wafers processed through the paths, calculating a mean value and variation of each group of the test results, wherein the mean value and variation of lot j of the wafers processed through path i are W(i,j) and &sgr;(i,j) respectively, providing weights for the lots of the wafers, wherein the weight for lot j of the wafers processed through path i is R(i,j), calculating estimates P of the paths, wherein the estimate of path i using the wafers from M
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and selecting one of the paths according to the estimates.
The present invention further provides an apparatus of tool matching for a semiconductor manufacturing process having a first and second path completed by serial combinations of tools for processing of wafers. The apparatus comprises means for providing a target value, means for obtaining a first and second test result of the wafers processed through the first and second path respectively, means for calculating differences between the first and second test result and the target value to obtain a first and second estimate respectively, and means for selecting one of the first and second path according to the estimates.
REFERENCES:
patent: 5128737 (1992-07-01), Have
patent: 6281696 (2001-08-01), Voogel
Chiou Hung-Wen
Tso Chia-Chun
Ladas & Parry
Niebling John F.
Promos Technologies Inc.
Stevenson André C.
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