Data processing: measuring – calibrating – or testing – Measurement system – Performance or efficiency evaluation
Reexamination Certificate
2005-05-03
2005-05-03
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system
Performance or efficiency evaluation
C702S058000, C324S765010
Reexamination Certificate
active
06889164
ABSTRACT:
A method of and apparatus for determining a defect-free semiconductor integrated circuit, such as a CMOS IC. The method includes a measurement step of selecting a defect-free CMOS integrated circuit (IC) from a group of CMOS integrated circuits by measuring quiescent power supply current (QPSC), a step of successively inspecting a test IC and the reference defect-free IC for resemblance for QPSCs, and a comparison and determination step of determining resemblance between QPSC data so that when the resemblance is high, the first and second ICs are determined to be defect-free ICs, and when the resemblance is low, the first and second ICs are determined to be defective ICs. The apparatus performs at least those steps.
REFERENCES:
patent: 5332973 (1994-07-01), Brown et al.
patent: 5392293 (1995-02-01), Hsue
patent: 5519333 (1996-05-01), Righter
patent: 5889408 (1999-03-01), Miller
patent: 5914615 (1999-06-01), Chess
patent: 6175244 (2001-01-01), Gattiker et al.
patent: 6342790 (2002-01-01), Ferguson et al.
patent: 8-271584 (1996-10-01), None
patent: 9-211088 (1997-08-01), None
patent: 2000-171529 (2000-06-01), None
M.C. Johnson, D. Somasekhar, and K. Roy, “Models and Algorithms for Bounds on Leakage in CMOS Circuits”, IEEE Tran. CAD IC Sys., vol. 18, No. 6, pp. 714-725, Jun. 1999.
A. Ferre and J. Figueras, “On Estimating Bounds of the Quiescent Power Supply Current for IDDQ Testing”, VLSI Test Sym., pp. 106-111, IEEE, 1996.
P.C. Maxwell and J.R. Rearick, “Estimation of Defect-Free IDDQ in Submicron Circuits Using Switch Level Simulation”, Int. Test Conf., pp. 882-889, IEEE, 1998.
A. Gattiker and W. Mary, “Current Signatures”, VLSI Test Sym., pp. 112-117, IEEE, 1996.
C. Thibeault, “On the Comparison of IDDQ and IDDQ Testing”, VLSI Test Sym., pp. 143-150, IEEE, 1999.
T.W. Williams, R.H. Dennard, R. Kapur, M.R. Mercer, W. Maly, “Iddq Test: Sensitivity Analysis of Scaling,” Int. Test Conf., pp. 786-792, Oct. 1996.
A. Gattiker and W. Maly, “Toward Understanding: Iddq-Only Fails,” Department of ECE, Carnegie Mellon University, Pittsburgh, PA.
A. Keshavarzi, C. Hawkins, K. Roy, and V. De, “Effectiveness of Reverse Body Bias for Low Power CMOS Circuits,” Microprocessor Research Labs, The University of New Mexico, and Purdue University, Intel Corporation, Hillsboro, OR 97124, USA.
A. Keshavarzi, K. Roy, and C. Hawkin, “Intrinsic Leakage in LOw Power Deep Submicron CMOS Ics”.
Hoff Marc S.
Kananen Ronald P.
Kim Paul L
Sony Corporation
LandOfFree
Method and apparatus of determining defect-free... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus of determining defect-free..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus of determining defect-free... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3426106