Coded data generation or conversion – Digital code to digital code converters – To or from nrz codes
Reexamination Certificate
2002-12-20
2004-02-24
Young, Brian (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from nrz codes
C341S058000
Reexamination Certificate
active
06696994
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to method and apparatus of modulating a series of data words into (d,k) constrained sequence in order to record onto a recording medium such as magnetic, magneto-optical, or optical disk.
2. Description of the Related Art
In general, when data is recorded onto a magnetic, magneto-optical, or optical medium, the data is modulated into a coded sequence matching the recording medium prior to the recording. However, if the coded sequence resulting from the modulation contains a direct current (DC) component, a variety of error signals such as tracking errors generated in control of a servo of the disk drive become prone to variations or jitter are generated easily.
The first reason for using said dc-free signals in recording onto a medium is that recording channels are not normally responsive to low-frequency components. The suppression of low-frequency components in the signal is also highly advantageous when the signal is read from an optical record carrier on which the signal is recorded in the track, because then continuous tracking control undisturbed by the recorded signal is possible.
A good suppression of the low-frequency components leads to improved tracking with less disturbing audible noise. For this reason it is thus desirable to make as many efforts to prevent the modulated sequence from containing a direct current component as possible.
In order to prevent the modulated sequence from containing a direct current component, control of a DSV (Digital Sum Value) has been proposed. This well-known method is explained briefly.
FIG. 1
shows a block diagram of a general coding system. The coding system includes a generator
10
generating a number of codeword candidates for each input data word; and a selector
20
selecting a codeword with the smallest DSV among the candidates.
FIG. 2
shows a detailed block diagram of the coding system. As shown in
FIG. 2
, the generator
10
includes an augmentor
100
and a plurality of NRZI coders
101
to
116
while the selector
20
includes a plurality of codeword memories
201
1
to
216
1
, and a plurality of DSV calculators
202
1
to
216
2
, and a selecting unit
220
.
The augmentor
100
generates for each input word a number of codeword candidates by combining mutually different digital words with the data word and then scrambles them individually. The codeword candidates can be generated simply by placing the mutually different digital words in front, middle, or rear of the input data word. If a 4-bit digital word is used 16 candidates are generated by the augmentor
100
. The NRZI coders
101
to
116
conduct NRZI pre-coding for the respective codeword candidates. The binary “zeros” outputted from each coder represent no (magnetic flux or electrical intensity) change, while binary “ones” represent transitions from one direction of recorded flux to the opposite direction.
The codeword candidates from the generator
10
are stored in the respective codeword memories
201
1
to
216
1
. Each of the DSV calculators
201
2
to
216
2
calculates DSV of the codeword candidate stored in a corresponding memory and adds the calculated DSV to a total DSV accumulated from previously selected successive codewords. Each finally-calculated total DSV is applied to the selecting unit
220
.
Then, the selecting unit
220
compares the inputted final DSVs each other from the DSV calculators
201
2
to
216
2
to determine the smallest final DSV. The codeword candidate associated with the determined final DSV is selected. Consequently, a codeword with the smallest DSV is outputted from the selector
20
. This process enables a series of codewords with the least DC component to be recorded onto a recordable medium.
However, if the number of consecutive “0”s within a codeword and the number of linking “0”s between the last “1” of the first codeword and the first “1” of the second in are not limited in the above modulating process, a codeword with relatively long “0”s may be selected. If such a codeword is chosen frequently, there will be too long an unbroken string of contiguous “0”s with no interspersed “1”s during reproduction, so that the clock regenerating phase-locked-loop (PLL) will fall out of synchronism, which possibly causes data error or reproduction fail.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a coding system being able to limit the number of consecutive “0”s between two “1”s in the process of generating a number of codeword candidates for each input data word and selecting a codeword candidate to suppress DC component.
An apparatus of converting a series of data word into a modulated signal in accordance with the present invention is characterized in that it comprises a generator generating for each data word a number of alternative sequences by combining mutually different digital words with the data word; a first calculator calculating a digital sum value for each alternative sequence; a second calculator calculating for each alternative sequence a penalty based on respective consecutive-zeros sections; and a selector selecting one alternative sequence for recording onto a recordable medium based on the calculated digital sum values and penalties.
A method of converting a series of data word into a modulated signal in accordance with the present invention is characterized in that it comprises the steps of: generating for each data word a number of alternative sequences by combining mutually different digital words with the data word; calculating, for each alternative sequence, a digital sum value and a penalty based on respective consecutive-zeros sections; and selecting one alternative sequence for recording onto a recordable medium based on the calculated digital sum values and penalties.
REFERENCES:
patent: 5506581 (1996-04-01), Ino
Kim Jin Yong
Suh Sang Woon
Birch & Stewart Kolasch & Birch, LLP
LG Electronics Inc.
Young Brian
LandOfFree
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