Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-04-02
2004-10-05
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185260
Reexamination Certificate
active
06801453
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices and more particularly to a read scheme for a programmable read only memory (PROM) cell having charge trapping dielectric material in the gate.
2. Description of the Related Art
Memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications, such as portable communication systems.
U.S. Pat. No. 5,768,192, issued to Eitan et al., teaches an apparatus for and method of programming and reading a programmable read only memory (PROM) having a trapping dielectric layer sandwiched between two silicon dioxide layers, as shown in FIG.
1
.
FIG. 1
illustrates a sectional view of a PROM cell constructed in accordance with Eitan's reference utilizing ONO as the gate dielectric. The PROM can be programmed to let electrons trapped in both sides of the silicon nitride layer
20
near the source
14
and the drain
16
(i.e. 2 bits/cell operation).
To sense or read the source
14
side charges, voltages are applied to the gate and the drain
16
while the source
14
and the substrate are ground, wherein the gate voltage is 3V and the drain voltage is 1.5V. In other words, the drain-to-substrate bias is 1.5V, the source-to-substrate bias is 0V, and the drain-to-source bias is 1.5V. The voltages for the drain
16
and the source
14
can be interchanged to read the drain side charges. The current for reading the source side charges, for example, might be influenced by the drain side charges. The more area that the depletion region of the drain-to-substrate junction covers the substrate surface under the drain side charges, the more stable the read current.
Larger drain-to-substrate bias is capable of extending the depletion region to cover more area under the trapped charges at the drain side. The larger depletion region avoids the trapped electrons interfering with the read current and makes the read current stable. Therefore, an instinct solution to provide a higher drain voltage. However, read disturb is caused when the drain-to-source bias is too large to make the amount of the drain side charges stable because of higher lateral electric field. That means that, after reading source side charges several times, the drain side charges, or the data stored at the drain side, might be unexpectedly changed.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a read scheme for a non-volatile memory that can read the trapped charges at one side while has less influence from those at the other side.
Another object of the present invention is to avoid read disturb during reading the non-volatile memory.
To achieve the above-mentioned object, the present invention provides a method of a read scheme for a non-volatile memory cell. The non-volatile memory cell has a substrate, a first source/drain, a second source/drain with a channel region therebetween, and a gate. The gate is located above the channel region separated therefrom by a nonconductive charge trapping material sandwiched between first and second insulating layers. The method comprises the steps of applying a first positive bias across the first source/drain and the substrate, applying a second positive bias across the second source/drain and the first source/drain, and applying a third positive bias across the gate and the first source/drain.
In addition, the present invention provides a method of a read scheme for a non-volatile memory cell. The non-volatile memory cell has a substrate, a first source/drain, a second source/drain and a gate. The gate is located above a channel region separated therefrom by a silicon nitride layer sandwiched between first and second silicon oxide layers. The method comprises the steps of applying a first voltage to the first source/drain, applying a second voltage to the second source/drain, applying a third voltage to the gate, and applying a fourth voltage to the substrate. The first voltage is higher than the second voltage, and the second and third voltages are higher than the fourth voltage.
REFERENCES:
patent: 5644533 (1997-07-01), Lancaster et al.
patent: 5768192 (1998-06-01), Eitan
patent: 5822243 (1998-10-01), Shone
patent: 6272050 (2001-08-01), Cunningham et al.
Lu Tao-Cheng
Tsai Wen-Jer
Yeh Chih-Chieh
Birch & Stewart Kolasch & Birch, LLP
Macronix International Co. Ltd.
Nelms David
Nguyen Thinh T.
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