Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
1999-04-13
2001-05-15
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S111000, C438S123000, C438S124000
Reexamination Certificate
active
06232148
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an improved semiconductor device and method for increasing semiconductor device density. In particular, the present invention relates to a device and method utilizing a leads-between-chip leadframe.
2. State of the Art
High performance, low cost, increased miniaturization of components and greater packaging density of integrated circuits have long been goals of the computer industry. As a general matter, semiconductor substrate assemblies, such as motherboards or function cards to be placed in a motherboard expansion bus slot, comprise a multitude of integrated circuit chips which are coupled to each other in order to make the assembly functional. For example, a central processing unit (“CPU”) or microprocessor and a plurality of memory devices or chips may be electrically coupled to each other in order to provide operational control for the semiconductor substrate assembly. Ordinarily, the CPU and the memory devices are proximate to each other on one surface or on opposing surfaces of the motherboard or function card. The terminals of the integrated circuit chips (CPU and memory chips) are coupled to each other by means of circuit traces disposed on or in the motherboard or function card and extending from one individual chip (bare or packaged) to another. However, this standard chip arrangement requires substantial surface area or “real estate” for positioning each integrated circuit chip on the circuit board. Thus, integrated circuit density on a circuit board or other carrier, for any given level of component and internal conductor density, is substantially limited by the space available for die mounting.
In order to maximize real estate utilization, vertical stacking or superimposition of integrated circuit chips or dice has become common practice. U.S. Pat. No. 5,012,323, issued Apr. 30, 1991 to Farnworth (“Farnworth”), teaches combining a pair of dice mounted on opposing sides of a leadframe. An upper die is back-bonded to the upper surface of the leads of the leadframe via a first adhesively coated, instilative layer. The lower die is face-bonded to the lower leadframe die-bonding region via a second, adhesively coated, insulative film layer. The wirebonding pads on both upper and lower dice are interconnected with the ends of their associated lead extensions with gold or aluminum wires. The lower die needs to be slightly larger than the upper die in order that the lower die bonding pads are accessible from above through an aperture in the leadframe, such that gold wire connections can be made to the lead extensions. However, this arrangement has a major disadvantage from a production standpoint, since the different size dice require that different equipment produce the different dice and assemble some with the lead frame or that the same equipment be switched over in different production runs to produce and assemble the different dice and leadframe. Moreover, the leadframe design employed by Farnworth employs long conductor runs between the die and the exterior of the package and the leadframe configuration is specialized and rather complex.
U.S. Pat. No. 5,291,061, issued Mar. 1, 1994 to Ball (“Ball”), teaches a multiple stacked die device that contains up to four dice, which device does not exceed the height of then current single die packages. The low profile of the device is achieved by close-tolerance stacking which is made possible by a low-loop-profile wirebonding operation and thin-adhesive layers between the stacked dice. However, Ball secures all of the dice to the same (upper) side of the leadframe, necessarily increasing bond wire length, even if some of the leads are bent upwardly, as disclosed. Moreover, Ball employs a die paddle to support the die stack, a technique which may require an extra die-attach step, and which increases the distance between the inner lead ends and even the lowermost die in the stack, resulting in longer bond wires.
U.S. Pat. No. 5,323,060, issued Jun. 21, 1994 to Fogal et al. (“Fogal”), teaches a multichip module that contains stacked die devices, the terminals or bond pads of which are wirebonded to a substrate or to adjacent die devices. However, the stacked configuration of Fogal results in relatively long bond wires and requires a supporting substrate carrying conductor traces.
Each of the stacked die configurations disclosed in the above references uses bond wires which give rise to a common problem of bond wire sweep. When encapsulating a bare die assembly, the die assembly is generally placed in a mold wherein a molten filled-polymer encapsulate material is injected into the mold to surround the die assembly as it conforms to the mold. However, the encapsulant flow front attendant to this process causes stresses on the bond wires. Since the molten encapsulating material is viscous, it tends to place forces transverse to at least some of the bond wires as the encasing material is injected into the mold. These directional forces cause the bond wires to flex which can, in turn, cause the bond wires to short with adjacent bond wires or bond pads.
An alternate method for lead attachment in a stacked die arrangement is the “leads over chip” (“LOC”) configuration. U.S. Pat. No. 4,862,245, issued Aug. 29, 1989 to Pashby, discloses a LOC configuration, wherein the inner lead ends of a standard dual in-line package (“DIP”) leadframe configuration extend over and are secured to an upper or active surface of the die through a dielectric layer. The bond wire length is thus shortened by placing the inner lead ends in close proximity to a central row of die bond pads, and the lead extensions purportedly enhance heat transfer from the die. However, the Pashby LOC configuration, as disclosed, relates to mounting and bonding only a single die.
U.S. Pat. No. 5,438,224, issued Aug. 1, 1995 to Papageorge et al. (“Papageorge”), discloses an integrated circuit package with a stacked integrated circuit chip arrangement placed on a circuit substrate. The stacked arrangement comprises a first flip chip and a second flip chip positioned face to face with a substrate interposed between the chips to provide electrical connection among the terminals of the flip chips and external circuitry. However, the Papageorge stacked arrangement uses a TAB or flex circuit substrate between the facing flip chips, and thus requires a separate mechanical support, such as a printed circuit board, for the assembly. The design also renders fabrication more difficult due to the lack of rigid support for the chips.
FIG. 1
of the drawings schematically illustrates a typical prior art leadframe
100
. The leadframe
100
comprises a plurality of lead fingers
102
and a die-attach paddle
104
. The shaded areas
106
are removed in the post-encapsulation trim and form process.
FIG. 2
illustrates the leadframe
100
utilized in a wire-bonded bare die assembly
200
. Components common to both
FIGS. 1 and 2
retain the same numeric designation. The bare die assembly
200
comprises a semiconductor die
202
having a plurality of bond pads
204
on an upper surface
206
of the semiconductor die
202
. The semiconductor die
202
is adhered by its back side (not shown) to the leadframe die-attach paddle
104
with an appropriate adhesive, such as a solder or an epoxy, as known in the art. The semiconductor die
202
achieves an electrical connection with the leadframe
100
with a plurality of bond wires
208
connected between each bond pad
204
and its respective lead finger
102
. In wirebonding, a plurality of bond wires are attached, one at a time, to each bond pad on the semiconductor die and extend to a corresponding lead or trace end on the printed circuit board. The bond wires are generally attached through one of three industry-standard wirebonding techniques: ultrasonic bonding—using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bonding—using a combination of pressure and elevated temperature to form a weld; a
Bruce Jeffrey D.
Habersetzer Darryl L.
Ma Manny Kin F.
Miller James E.
Roberts Gordon D.
Bowers Charles
Brewster William M.
Micro)n Technology, Inc.
TraskBritt
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