Method and apparatus including a shared resource and multiple pr

Details Method and apparatus including a shared resource and multiple pr Method and apparatus including a shared resource and multiple pr

1996-11-27

1999-03-16

An, Meng-Ai T.

39520043, 39520044, 39520045, G06F 1300

Patent

active

058840559

ABSTRACT:
An integrated cached disk array includes host to global memory (front end) and global memory to disk array (back end) interfaces implemented with dual control processors configured to share substantial resources. The dual processors each access independent control store RAM, but run the same processor independent control program using an implementation that makes the hardware appear identical from both the X and Y processor sides.

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