Method and apparatus in a data processor for selectively disabli

Details Method and apparatus in a data processor for selectively disabli Method and apparatus in a data processor for selectively disabli

1983-11-07

1986-02-25

Thomas, James D.

Boots, shoes, and leggings

G06F 104

Patent

active

045731179

ABSTRACT:
A method for allowing the user of a data processor having a power-down instruction to selectively disable the power-down instruction. In the preferred circuit, the user stores a special code in a control register indicating that the power-down instruction is to be disabled. Upon a power-down instruction being subsequently executed, the processor is precluded by the code from turning off the oscillator which provides the system clocks. The processor thus proceeds to the next instruction as if the power-down instruction were a "no-operation" instruction.

REFERENCES:
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patent: 4279020 (1981-07-01), Christian et al.
patent: 4293927 (1981-10-01), Hoshii
patent: 4365290 (1982-12-01), Nelms et al.
patent: 4381552 (1983-04-01), Nocilini et al.

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